Double-Sampling Front-End Scaling

CMOS has been the leading technology for building integrated circuits for many years [1]. Owing to the scaling of this technology more functionality and faster devices become avail- able with every new generation. The shrinking feature sizes and lower supply voltages offered by scaled CMOS technologies reduce the power consumption of most processing blocks while enabling faster operation. This reduction in power and increase in speed usually happens to digital systems. If the same paradigm can be applied to IOs, a huge reduction in power con- sumption and area of transceivers could be achieved, which would allow for higher numbers of IOs with higher data rates per chip. The combination of higher number of IOs and higher data rates per IO leads to a huge improvement in the overall chip-to-chip bandwidth.

This section examines how the performance of the proposed optical receivers will scale with advances in CMOS technology. We look into the challenges and problems introduced to the double sampling front-end design in deep sub-micron CMOS.

Figure 5.11: Optimum sampling capacitor size,CS versus the photodiode capacitance,CP D.

The removal of the high-speed gain stage in the proposed double sampling integrating front-end makes it a promising candidate for CMOS technologies that commonly have a poor gain-bandwidth product. While the digital behavior of the front-end prompts a good scalability, there are many subtle design issues as we move to more advanced technologies. In this section, we examine the scaling behavior of the double sampling/integrating front-end with respect to sensitivity, bandwidth, power consumption, and dynamic range.

5.2.2.1 Sensitivity

Our discussion in Section 5.1, and Equation 5.8 show that the required optical power for this receiver, strongly depends on the diode capacitance, Cp and the sampling capacitance,

Cs. If these capacitances stay constant, the input optical power increases linearly with the

data rate as the technology scales. This becomes particularly problematic as the number of transceivers in an array of parallel IOs increases. As a result of this effect, in order to accommodate a larger number of IOs, larger optical power has to be provided by optical transmitter. In order to alleviate this problem, both the photodiode capacitance and the sampling capacitance have to be scaled. Figure 5.11 shows that the optimum value for CS

Recent advances in design of photodiodes promise diode capacitances lower than 10fF [141, 142]. In Section 5.2.3 we will discuss the effects of the photodiode capacitance scaling on the performance of the RC front-end double-sampling receiver.

5.2.2.2 Data Rate

Scaling the feature sizes in CMOS technology with rateαresults in an increase in the switch- ing speed of transistors linearly with almost reverse relation, α−1. The fundamental limit on the bandwidth of the double-sampling receiver is the aperture time of the samplers. For higher data rate theRSCS time constant should scale down, where RS is the ON resistance

of the NMOS switch. For the optimum sensitivity we need to keep capacitance CS con-

stant. Thus, for higher data rates the resistance RS should scale down. This is possible by

keeping the width of the pass-transistor (in microns) constant, while the length is equal to the minimum channel size of the technology. As technology scales, the transistor channel length scales down and hence RS also decreases. Similarly the on-chip clock frequency for

generation of multi-phases increases and allows higher data rates.

In addition to the sampler aperture time, the photodiode capacitance has a significant impact on the maximum possible data rate of this receiver which is mandated through the trade-off between sensitivity and data rate. This will be discussed in more detail in Section 5.2.3.

5.2.2.3 Power Consumption

The power consumption in high-speed IOs is the most important issue. Increasing the number of IOs per chip is possible only if the power consumption per IO reduces. In digital systems the power consumption is dominated by the dynamic power for switching internal capaci- tances, P = CV2_{f, as well as the leakage dissipations. As technology scales, the dynamic}

power consumption of a similar block reduces with a factor of almostα2_{. This is because the}

capacitances reduce with α, the power supply reduces with α, and the frequency increases with α−1_{. For the proposed front-end, the capacitances of the samplers/comparators are}

dictated by the sensitivity requirements and hence the photodiode capacitance size. There- fore, the power consumption of the front-end scales only as α. It should be noted that the power consumption in the following stages (sense-amplifier and SR latch), wires, and clock generation circuits scale as α2_{. For instance, scaling to 28nm technology with 1V power}

supply and constant diode capacitance, results in a power reduction of almost a factor of two for the same data rate, which agrees well with simulations. It is important to mention that the supply scaling has slowed down. As a result, the front-end power will decrease at a slower rate; however as long as scaling results in smaller feature size and hence parasitic capacitance, power reduction can be achieved by employing advanced technologies.

5.2.2.4 Dynamic Range

The dynamic range of the proposed double-sampling receiver relies on the size of the resis- tance in the front-end. As mentioned earlier, this resistor at the front-end limits the voltage to Vdd −RI1. The interesting point about this technique is that as long as the input time

constant (RC) is much larger than the bit time (Tb) the resulting double-sampled voltage is

constant and equal to

VP Dmax−VP Dmin =RI1max =RρPmax. (5.23)

Therefore, by adjusting the input resistor, different optical powers can be accommodated. The maximum optical power that can be received without sacrificing the sensitivity occurs when the resistor size becomes so small that the input time constant is comparable to the bit time. On the other hand, the minimum input voltage is limited by the fact that the PMOS sampling switches will introduce large on-resistance at low input voltages. As the time constant of the sampler exceeds a fraction of the bit time, a larger error will be generated. Due to the scaling of Vdd, the input voltage range becomes smaller and smaller. For a 28nm

technology with Vdd = 1 this range is about 400mV for a total capacitance of 250fF and

20Gb/s data rate. This translates to a minimum of 1KΩ of resistance and about -3dBm maximum optical power. According to simulation, the receiver operates at higher input

optical powers. This is due to the fact that, even though the sampled voltage is smaller than the actual voltage, the double-sampled voltage is quite large. The measurement results agree with this observation and the receiver operates with 0dBm of received optical power.