Cautions 1. Be sure to check with NEC Electronics that the ASIC product development information (checksheet) you are planning to use is the latest version. Do not use this description example for actual
2. The load capacitance value may change in order to improve the accuracy of the actual wiring length
2.9.6 DPLL block
(1) Blocks used
(2) An initialization pattern has been createdNote...
(Execute simulation using the initialization pattern and check that there were no mismatches.) (3) In the initialization pattern, all the I/O buffer modes have been securedNote...
(4) If the DPLL’s external pins have I/O buffers, the input pins are fixed to input and the output
pins are fixed to output when TMD0, TMD1, (TMD2) are in DPLL unit test modeNote...
(Ensure the 3-state buffer is ON.)
(5) Clock (RZ) and modulation (NRZ) are not used for external pin connected to DPLL
in the initialization patternNote...
(Do not make a timing specification.)
(6) All output pins of the initialization pattern except the TOUT pin are “don’t care”
(except oscillation output signal)Note...
(7) The DPLL’s input and output pins can be accessed directlyNote...
If not, verification and approval of special requests, etc., by NEC Electronics are required before interfacing.
(8) The RCLK, TMD0, TMD1, TMD2, TMD3, and TOUT pins do not share signal lines with other signalsNote...
(This does not apply to sharing TMD0 to TMD3 with pins with the same function when using multiple DPLLs)
(a) When using a DPLL together with NEC_SCAN, can the above pins be accessed without being affected by other external pins? ...
If not, add information to pin fixing file regarding 2.9.8 Alternate use as scan path and boundary scan and 2.9.9 Scan path.
(b) It is confirmed that the output signal of the TOUT pin is not used in the internal circuitNote...
If not, verification and approval of special requests, etc., by NEC Electronics are required before interfacing.
(9) The test pattern (DC, LFT) was generated in through path mode and reset mode onlyNote...
(10) A dedicated buffer (FI0P/FI0Q) is used for RCLK (H01)Note...
(11) A function error does not occur as a result of creating and simulating the pattern
for checking DPLL connectionNote...
(12) Interface data
Submit the .dpmodechk file and .slg file in addition to normal interface data.
Note If this item is satisfied, check the box. For any boxes left unchecked, please write proposed countermeasures.
SAMPLE
Enter the following information about the DPLL block.
(1) Enter the block names, Instance names and number of DPLL blocks used.
(2) Indicate whether an initialization pattern has been created. An initialization pattern must be prepared.
(3) In the initialization pattern, in order to perform a stable the DPLL test, it is necessary to fix the mode of the I/O buffers not related to the DPLL, so indicate that these buffers have been mode-fixed.
(4) When testing the DPLL, the mode of the external pins must be fixed to input mode when connected to input pins and output mode when connected to output pins, so indicate that these pins are fixed to either input or output (Ensure the 3-state buffer is ON).
(5) In the DPLL test initialization pattern, clock and modulation cannot be used for the external pin connected to DPLL.
Indicate that a clock (RZ) or modulation (NRZ) is not being used (Do not make a timing specification).
(6) The final patterns of output pins other than TOUT pin in the initialization pattern must all be “don’t care” for performing DPLL test. Check if this is the case and mark accordingly.
However, the oscillation output signal when the oscillator is included must not be “don’t care”.
(7) To test the DPLL, the input control pin and TOUT pin must be accessed directly, so indicate whether the input and output pins can be accessed directly.
(8) Indicate that the RCLK, TMD0, TMD1, TMD2, TMD3, and TOUT pins do not share signal lines with other signals (this does not apply to sharing TMD0, TMD1, TMD2, and TMD3 with pins with the same function when using multiple DPLLs).
(a) When using a DPLL together with NEC_SCAN, check and indicate that the above pins can be accessed without being affected by other external pins.
If they can’t, add the required level information of the other external pins to the scan path pin fix file.
(b) Check if the output signal of the TOUT pin is not used by the internal circuit, and mark accordingly.
If not, verification and approval of special requests, etc., by NEC Electronics are required before interfacing.
(9) Indicate that the PLL or NEC test mode is not being used in the test pattern (in the user pattern, this only applies to through-path mode or reset mode).
(10) A dedicated buffer must be used for the external pin connecting RCLK. Indicate that this is the case.
(11) Indicate that function errors do not occur when executing simulation after creating the pattern for checking DPLL connection. Use ALBATROSS for OPENCAD V5.4 or later and ALBATROSS or LOGPAT for OPENCAD V5.3 as the pattern format at this time.
(12) Please submit .dpmodechk and .sig for DPLL connection verification simulation, in addition to regular materials, as interface data.
SAMPLE
(13) Pin correspondence table
(a) Either submit the .pinf file, or enter (c) pin correspondence table.
(b) If multiple DPLLs are included during .pinf file submission, enter the .pinf file correspondence.
DPLL block name F9E6 Interface name DPLL1 .pinf file name F9E6.pinf DPLL block name F9E4 Interface name DPLL2 .pinf file name F9E4.pinf
(c) Pin correspondence table (if multiple DPLLs are included, make several copies of this sheet and enter the information as required.)
DPLL block name F9E6 Instance name DPLL1
Pin Name
SAMPLE
(13) Pin correspondence table
(a) Either submit the .pinf file, or enter (c) pin correspondence table.
(b) Enter the DPLL block name and interface name corresponding to the .pinf file.
(c) Enter the required information in the pin correspondence table. If multiple DPLLs are included, make several copies of this sheet and enter the information as required.
SAMPLE
2.9.7 Megamacro
(1) Blocks used
Remark Always initialize the megamacro after inserting the initialization pattern in each megamacro into the start of test patterns such as DC and LFT. (In the case of H, a BUS configuration for the megamacro outputs is not possible)
• In the case of CSE = L, what is the circuit configuration of the megamacro outputs?
(a) The megamacro outputs have a BUS configuration ...
(b) Megamacro outputs are received via a gate and Hi-Z disappears. ...
(This is basically prohibited in EA-9HD. Use a bus holder in this case.)
(3) Direct signals have been added from input pins for all the inputs of the megamacroNote ...
(Do not invert signals or pass them through a sequential circuit)
(4) Direct monitoring is possible at output pins for all the outputs of the megamacroNote ...
(Do not invert signals or pass them through a sequential circuit)
(5) A megamacro single-unit test setting pattern has been generatedNote ...
Ensure that the megamacro single-unit test pattern conforms to next (a) to (f) interface conditions.
(a) All the final patterns of output pins other than those of megamacros are “don’t care”
(except for the oscillation output signal)Note ...
(b) Neither clock (RZ) nor modulation (NRZ) is usedNote...
(c) The I/O buffer mode has been securedNote ...
(d) The internal circuits other than those of the megamacro have been initializedNote ...
(e) There is no Hi-Z or unknown inputNote ...
(f) There were no mismatches as a result of the simulation before placement and routingNote...
(6) Is a test pattern required for setting (3) and (4) above? ... YES NO In the case of YES, incorporate it in the single unit test setting pattern.
(7) The “Megamacro Single Unit Test Specification Document” from the megamacro design
manual has been submittedNote ...
(If not, include it with this manual)
• The required items for the megamacro to be used should be included in the above document.
Note If this item is satisfied, check the box. For any boxes left unchecked, please write proposed countermeasures.
Remark If there are any details regarding the megamacro test circuit configuration that require special attention, please enter them here.
A bidirectional buffer is used and ID0 to ID7 and OD0 to OD7 are used in common.
SAMPLE
Enter the following information about megamacros.
(1) Enter the name and number of the megamacro blocks used
(2) The configuration of the megamacro output block differs depending on the level of the CSE pin, so indicate that the level of the CSE pin is fixed to either H or L.
In the case of CSE = L, indicate whether the megamacro outputs are configured as a BUS or as a gate (refer to the relevant design manual for details of the circuit configuration).
(3) For the megamacro single-unit test using the tester, direct signals must be added from input pins for all the inputs. Check the circuit and indicate that this is the case.
(4) For the megamacro single-unit test using the NEC tester, direct monitoring must be possible at output pins for all the outputs. Check the circuit and indicate that this is the case.
(5) When creating a megamacro single unit test design pattern, check and indicate that items (a) to (f) are all checked.
(6) When performing the megamacro single-unit test, in order to transfer external signals to megamacro inputs without inverting them when gates, etc., have been inserted into the signal lines of the test pins, a setting pattern is required. Indicate whether a test pattern for setting (3) and (4) is required.
(7) Indicate whether the required sections of the “Megamacro Single Unit Test Specification Document” in the megamacro version of each design manual have been copied and submitted with the required items entered (items such as the instance names and pin reference table are required specifications and therefore must be prepared).
For example, if a specific method such as sharing the megamacro data input and output is being used, enter this information.