Cautions 1. Be sure to check with NEC Electronics that the ASIC product development information (checksheet) you are planning to use is the latest version. Do not use this description example for actual
4. Check these columns for the setting pattern and initialization pattern
2.9.2 RAM block
(1) About the RAM block
(a) Blocks used
(b) Compiled RAM is used ...
(c) If compiled RAM is used, there are an even number of wordsNote...
(d) All RAMs used are RAM with BIST (use of basic RAM only is prohibited)Note...
(e) The TE pin is directly accessed without inverting the logic from an external pin in the
case of G/A and connected to TEB via an inverter in the case of EANote...
(f) In test mode (TE = L), the TIN and TOUT pins are directly accessed without inverting
the logic from external pinsNote...
(g) There is a test output pin (TOUT) provided for each of the RAMs usedNote...
(h) If multiple RAMs are used, the TE and TIN pins are common to all the RAMsNote...
(i) There are no patterns that access non-existent addressesNote...
(This does not apply to cell-based type high-density synchronous compiled RAM)
(j) TE/TEB of RAM for all test pattern data is not in test modeNote...
(k) A high impedance prevention circuit for normal mode is includedNote...
If it is not included, be sure to include a prevention circuit, otherwise the tester may
malfunction due to current flow, which may adversely affect shipping (embedded array only).
(l) The instance names of the metalization wafer and base wafer are the same ...
If they are not the same, submit the instance correspondence of the upper and base wafers (embedded array only).
(m) Enter the names of the RAM test pins.
TE/TEB (1 pin) TENB
TIN (1 pin) TESTI
TOUT (number of RAMs used) TOUT0, TOUT1
(n) There were no mismatches in the RAM check resultsNote...
All the boxes from (c) to (n) should be checked. Be aware that if one or more of these items are not checked, you may be requested to modify the circuitry at the test program creation stage (final development stage).
(o) Interface data
Submit the .rpi file in addition to normal interface data.
Note If this item is satisfied, check the box. For any boxes left unchecked, please write proposed countermeasures.
SAMPLE
(1) Enter the following information about the RAM block.
(a) Enter the RAM block type name, as well as the number of bits, number of words, and number of RAM blocks used.
(b) Indicate whether compiled RAM is used.
(c) Odd words are prohibited, so indicate that there is an even number of words.
(d) Check and indicate that all RAMs used are RAM with BIST.
Change to RAM with BIST because the use of basic RAM only is prohibited.
(e) Because the TE (TEB) pin must be directly accessed without inverting the logic from an external pin and connected via an inverter in the case of the EA-9, 9HD Series, indicate that this is the case.
(f) In test mode (TE = L), because the TIN and TOUT pins must be directly accessed without inverting the logic from external pins, indicate that this is the case.
(g) Because a test output pin (TOUT) must be provided for each of the RAMs used, indicate that this is the case.
(h) If multiple RAMs are used, because the TE and TIN pins must be common to all the RAMs, indicate that this is the case.
(i) In the EA-9, 9HD Series, because there can be no patterns that access non-existent addresses, indicate that this kind of pattern does not exist.
(j) Check whether TE/TEB is not in test mode for all patterns and mark accordingly.
(k) Check and indicate whether a high-impedance prevention circuit for normal mode is included. If it is not included, be sure to include a prevention circuit, otherwise the tester may malfunction due to current flow, which may adversely affect shipping (embedded array only).
(l) Check and indicate that instance names of metalization wafer and base wafer are the same.
If they are not the same, submit the instance correspondence of the upper and base wafers (embedded array only).
(m) Enter the names of the RAM test pins (TE, TIN, TOUT). (Enter one pin for TE and TIN. Because the TOUT pin cannot be shared in a gate array, enter one pin per RAM used.)
(n) Execute the RAM check and check and indicate that there were no mismatches in the result.
SAMPLE
(2) RAM initialization pattern (pattern for RAM single-unit test)
If there were no mismatches in the RAM check results, you do not need to fill out (a) to (e).
(a) If signals pass between the test pins and RAM block via an internal gate, the logic of this internal gate is set to the RAM’s test mode in the final pattern of the user-generated test pattern (Note that signals cannot pass through a sequential circuit.)Note...
(b) If there are bidirectional or 3-state pins (this includes all bidirectional and 3-state pins), enable is secured for these pins in the final pattern of the user-generated test patternNote...
• If any bidirectional or 3-state pins are being used as test pins, set the TE and TIN pins to input mode (EN = L) and the TOUT pin to output mode (EN = H) in the initialization pattern.
(c) If there is an internal bus in the LSI (this includes all in-circuit internal buses), that bus is neither shorted nor in a floating state in the final pattern of the user-generated test patternNote...
(d) If there is a sequential circuit in the LSI (this includes all in-circuit sequential circuits), the output of that sequential circuit is stable in the final pattern of the user-generated test patternNote...
Remark Regarding (d), the output should be stable so as to stabilize the LSI’s internal status and improve the accuracy of the RAM test.
If any of (a) to (d) above were not checked, an initialization pattern will be required for that item.
(e) Is an initialization pattern required for any of the above items? ... YES NO
• In the case of YES, please enter the following information.
<1> Neither “X” nor “Z” has been entered for the inputNote...
<2> The expected output value is “don’t care” Note...
<3> Initialization pattern range 19,990 Pattern to 20,000 Pattern
Note If this item is satisfied, check the box. For any boxes left unchecked, please write proposed countermeasures.
SAMPLE
(2) Enter the following information about the RAM initialization pattern (pattern for RAM single-unit test)
(a) The tester automatically inserts the RAM test pattern behind the DC pattern. Therefore, if signals pass between the RAM test pins and RAM block via an internal gate, because the logic of this internal gate must be set to the RAM’s test mode, indicate that this is the case (for the RAM test mode pattern, refer to the design manual).
(b) If there are bidirectional or 3-state pins, because these pins’ enable must be secured in the final test pattern of the DC pattern, indicate that this is the case.
(c) If there is an internal bus in the LSI, because bus short or floating states must be suppressed, indicate that the bus is neither shorted nor floating.
(d) If there is a sequential circuit in the LSI, because the RAM test may not be performed normally, indicate that the output of that sequential circuit is stable in the final pattern of the DC pattern.
(e) Indicate whether an initialization pattern is required for any of items (a) to (d). If YES, enter the following information (<1> to <3> below).
(If any of items (a) to (d) were not satisfied, then an initialization pattern is required.)
<1> If either X or Z is input for the RAM initialization pattern input, because a stable test may not be able to be performed, indicate that X or Z has not been input.
<2> Indicate that the status in the RAM initialization pattern is “don’t care” (mask status). This must be satisfied, because if the initialization pattern is not masked, the test may be defective.
<3> Because the RAM initialization pattern must be added to the end of the DC pattern, check that this is the case, and enter the pattern range of the RAM initialization pattern (this is not the pattern for checking connection (8 patterns)).
SAMPLE
2.9.3 ROM
(1) Blocks used
(2) Interface data
Submit the .nincf file in addition to normal interface data.
Block Name (Instance Name)
C$0010020 C$0020030
Block Type (Function)
J14F J14H
NINCF File
NINCF0 NINCF1
SAMPLE
Enter the following information about the ROM block.
(1) The name (instance name) and type (function name) of the ROM block being used, and the name of the NINCF file corresponding to that block.
Remark Note that in cases when there are multiple ROM blocks of the same type, if the name (instance name) and type (function name) of the ROM block is erroneous, the ROM code merge will not be executed correctly.
SAMPLE
(b) How many test patterns are there? ... 1
(2) Details of simulation using pattern for high-speed function test
(a) Simulation was performed under the following conditionsNote 1...