DWT CRS MISC HARDWARE UTILISATION

To verify that the DWT CRS MISC architecture can actually operate in the FPGA, a hardware implementation was performed onto a FPGA. This is done by writing the VHDL code that described the DWT CRS MISC architecture and performed a hardware implementation onto the Xilinx Spartan-3L FPGA. The hardware utilisation for such implementation is discussed in Section 4.3.1. Initial input image data was set in the memory such that it allowed the programmed DWT CRS MISC architecture to process the data and then produced the corresponding encoded data. After that, the MISC architecture produced encoded data were compared with the MATLAB generated encoded data. By comparing the data, both the encoded data produced from the DWT CRS MISC architecture and the MATLAB generated encoded data were of the same values. Therefore, this verified that the DWT CRS MISC architecture operates and processes the input image data correctly.

4.3.1 DWT CRS MISC in FPGA

The hardware utilisations for the proposed DWT CRS MISC architecture implemented onto Xilinx Spartan-3L FPGA was studied. This was obtained by synthesising the developed DWT CRS MISC architecture in the Xilinx ISE Design Suite 11.5. For this implementation, the MISC architecture required a total of 144 Slices (i.e. 94 Flip-Flops, 248 LUTs, 2 Block RAMs), which is shown in Table 13.

Note that in Spartan-3L FPGA, each of the Slices contains of 2 Flip-Flops and 2 Four-Input LUTs [146] [147]. Besides synthesizing into one type of FPGA platform, the DWT CRS MISC architecture is also considered for Xilinx Virtex-II and Xilinx Spartan-3E. The hardware utilizations of the DWT CRS MISC are 142 Slices (i.e. 92 Flip-Flops, 225 LUTs, 2 Block RAMs) and 129 Slices (i.e. 66 Flip-Flops, 223 LUTs, 1 Block RAMs). Different FPGA platform was also considered because it is used for comparison of existing method with the same FPGA family.

Table 14 shows that there are 6 existing techniques that were previously developed for WSNs, whereby they either performed compression, encryption and error corrections. Some of the listed techniques or systems performed the aforementioned techniques separately rather than in a single architecture. For example,

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the Cordic Loeffler Discrete Cosine Transform (CL-DCT) occupied 1,060 Slices in Xilinx Spartan-3L [25]. The Low-Density Parity-Check (LDPC) error correction encoder utilized a total of 870 Slices in Xilinx Virtex-II [98].

Table 13 Hardware utilisation of DWT CRS MISC architecture in Spartan-3L FPGA.

Components Quantity Total Usage

Slices 144 13,312 1.08%

Flip-Flops 94 26,624 0.35%

4-Input LUTs 248 26,624 0.92%

- Logic 226 - -

- Route-thru 22 - -

- Dual Port RAMs 0 - -

- Shift Registers 0 - -

Bonded IOB 26 221 26.70%

Block RAMs 2 32 6.25%

GCLKs 2 8 25.00%

For the Reed Solomon (RS) error correction, the synthesised RS Linear Feedback Shift Register (LFSR) method [17] shown in Table 14, required hardware utilisation of 415 Slices and the power consumption of 198.9mW. As for the developed RS MISC architecture, it only required 161 Slices and 164.2mW. It can be seen that the RS MISC architecture has 61.2% lower hardware utilisations and 17.4%

lower power consumption as compared with the RS LFSR method of hardware implementation.

Combining the encryption and error correction modules together, with the AES MISC [148] and followed by the RS MISC, would require a total of 480 Slices.

The combined AES MISC and RS MISC may required power consumption of at least 199.7mW, which is contributed by the AES MISC. The stated power consumption have not included the power consumed by the RS MISC and it may be even higher than the stated value. This method of implementing the image processing system has large amount of hardware utilisation and require relatively high power consumption.

Instead of combining two separate modules together, a CRS MISC architecture was developed that uses the single code of encryption and error correction code (CRS coding scheme). The developed CRS MISC architecture only required a total of 155 Slices and power consumption of 167.3mW. It can be seen that using single code of

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encryption and error correction code is better than using two different modules in terms of the hardware utilisations and power consumption.

Table 14 Hardware utilisations of developed and existing method used in similar FPGA technology (Spartan-3, Virtex-II) for WVSNs/WSNs.

Designs Functions Slices Flip-Flops

CRS MISC Encryption,

Error Correction 132 83 209 1 N/A

CRS MISC Encryption,

Error Correction 120 56 216 1 178.9

RS MISC Error Correction 124 61 221 1 178.9

ECBC [21] Encryption,

Error Correction 1,691 Not Mentioned

CRS MISC Encryption,

Error Correction 155 87 269 1 167.3

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4.3.2 DWT CRS MISC: Further Improvements

For further improvements, in hardware utilisation and power consumption, the developed DWT CRS MISC architecture was also considered for Xilinx Spartan-6 FPGA implementation. The hardware utilisation of the DWT CRS MISC architecture that was synthesized in Xilinx Spartan-6 FPGA, required a total of 66 Slices (i.e. 87 Flip-Flops, 176 LUTs, 2 Block RAMs). Lower hardware utilisation (in terms number of Slices) was expected for the implementation of the MISC architecture is because each Slices in the Spartan-6 FPGA contains of 8 Flip-Flops and 4 Six-Input LUTs [150], which is more than the number of Flip-Flops and LUTs in each Slices for the Spartan-3L FPGA. The hardware utilisation for the developed DWT CRS MISC architecture to be implemented onto the Spartan-6 FPGA is shown in Table 15.

Therefore, there is a huge reduction in hardware complexity if the developed DWT CRS MISC architecture to be implemented into the Spartan-6 FPGA.

In Table 16, the power consumption for the synthesised DWT CRS MISC architecture in two different type of FPGAs were estimated using the Xilinx XPower Analyzer 11.5. The total power consumption for MISC architecture in Spartan-3L FPGA was 167.29mW and Spartan-6 FPGA was 21.63mW. The differences in power consumption between these two technologies of FPGA is because that the Spartan-3L is 90nm FPGA [151] and the Spartan-6 is 45nm FPGA [152]. Since there is improvement on the technology of the FPGA, the Spartan-6 FPGA has 87.1% lower power consumption as compared to Spartan-3L FPGA [152]. Therefore, there is an great improvement in power consumption of the DWT CRS MISC architecture when it will be implemented onto the Spartan-6 FPGA.

Table 15 Hardware utilisation of DWT CRS MISC architecture in Spartan-6 FPGA.

Components Quantity Total Usage

Slice 66 2,278 2.90%

Flip-Flops 87 18,224 0.48%

6-Input LUTs 176 9,112 1.93%

- Logic 171 - -

- Route-thru 5 - -

- Memory 0 - -

Bonded IOB 26 232 11.21%

Block RAMs 2 32 6.25%

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In Table 17, it can be seen that there are at least 54.2% reduction in number of hardware utilisations when the developed RS MISC, CRS MISC and DWT CRS MISC architectures were synthesised into Spartan-6 FPGA. The great amount of reduction in hardware utilisations is because the Spartan-6 FPGA uses the 6-Input LUTs required less LUTs for the same implementations in Spartan-3L FPGA which uses the 4-Inpu LUTs [153].

Table 16 Xilinx XPower estimated power consumption of DWT CRS MISC architecture.

Power (W)

Spartan-3L Spartan-6

Clocks 0.00100 0.00076

Logics 0.00018 0.00007

Signals 0.00031 0.00003

IOs 0.02042 0.00007

BRAMs 0.00013 0.00080

Total Quiescent Power 0.14525 0.01989 Total Dynamic Power 0.02204 0.00174

Total Power 0.16729 0.02163

Table 17 Hardware utilisations of developed and existing method in Spartan-6 FPGA for WVSNs/WSNs.

Designs Functions Slices Flip-Flops

Crypto-Processor [117] Encryption 4,828 Not Mentioned

Not

Mentioned 19 17.0

RS MISC Error Correction 60 82 167 1 17.4

CRS MISC Encryption,

Error Correction 60 77 160 1 21.3

Table 17 shows the Crypto-Processor encryption required a total of 4,828 Slices [117]. As for the developed DWT CRS MISC, it only takes 1.3670% hardware utilization of the Crypto-Processor. This is a huge reduction in hardware utilizations compared to the Crypto-Processor. As a result, the developed DWT CRS MISC architecture has a low hardware utilisations as compared to the different existing

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techniques used in compression, encryption and error correction for WVSNs/WSNs.

Meanwhile, the DWT CRS MISC has the capabilities in reducing large amount of image data, providing data security and data reliability combined together in a single architecture with low hardware utilisations.