Dynamic element matching is used to convert mismatch errors into random noise. This is achieved through shuffling of unit elements such that static mismatch is randomized. Depending on the used random sequence errors can be shaped to white noise or have noise-shaping property, similar toΣ∆
converters [120]. For SAR ADCs DEM can be used to alleviate errors of the unit capacitors in the CDAC. In this way, we can allow more mismatch by choosing a small unit capacitance such that the total sampling capacitance is kept small.
The implemented DEM uses a barrel shifter to shuffle the unit elements.
Figure 5.3 shows a 4 bit example where elements are chosen in a cyclic manner. The start pointer is determined by a random sequence. The first half of all elements are chosen for MSB switching, the next quarter elements are for MSB−1, and so on.
DEM can be applied to all bits or only the first NDEMMSB. This gives us a tradeoff between DEM complexity and linearity improvement. A barrel shifter is used to lower complexity compared with fully-randomized shuffling.
For example, with NDEM = 5 the barrel shifter has only 31 possibilities compared with 31! = 8.22×1033for fully-randomized shuffler.
Figure 5.4 demonstrates DEM performance using behavioral simula-tion results of an 8 bit SAR ADC for different NDEM. Results for NDEM= 1
Step n
Figure 5.3:The implemented DEM choses unit elements in a cyclic manner. The start pointer is determined by a random sequence.
is equivalent to no DEM used. Multiple mismatch runs are performed for each simulation point.Figure 5.4(a)shows that cyclic and fully-randomized shuffling have similar performance. Only for NDEM= {7,8} we notice a small advantage.Figure 5.4(b)compares INL for 1–10 % unit mismatch. From Eq. (2.11)we know that INL must be <0.1 LSB for 10 bit performance. Fig-ure 5.4(c)shows SFDR for 10 % unit mismatch.
For a compromise between performance and complexity, NDEM= 5 has been chosen for this design. Even with a very conservative estimate of 10 % mismatch, most samples should achieve 10 bit linearity. Mismatch data were not available at design time because we used custom-built capacitors and due to the new technology.
For NDEM= 5, five CDAC signals are connected to 31 unit capacitances.
This means that it is not necessary to use a conventional 31 bit-to-31 bit barrel shifter. A simplified barrel shifter can be used with a reduced num-ber of multiplexers. A conventional barrel shifter requires NDEMlevels of multiplexers, where each level shifts by 2nbits with n = 0,..., NDEM−1. This requires NDEM(2NDEM−1)multiplexers to be implemented.Figure 5.5 illus-trates how a conventional barrel shifter can be simplified when it is used for SAR ADCs. Some combinations are redundant and can be collapsed to a single multiplexer. The number of multiplexers that can be saved is
Nlev
where Nlevis the number of levels to be optimized. Nlevmust be < NDEM−1.
5.3 Reference ADC 107
1 2 3 4 5 6 7 8
Number of MSB shuffled NDEM 0.1
1
SigmaINL[LSB]
Cyclic Shuffle Fully Random Shuffle
(a) Cyclic (numpy.roll) and fully-randomized (numpy.random.shuffle) unit element shuffling achieve similar performance (100 runs per point).
1 2 3 4 5 6 7 8
Number of MSB shuffledNDEM 0.01
0.1 1
SigmaINL[LSB]
10% Mismatch 5% Mismatch 1% Mismatch
(b)INL performance with different unit mismatch (50 runs per point).
1 2 3 4 5 6 7 8
Number of MSB shuffledNDEM 50
60 70 80
SFDR[dB]
10% Mismatch
(c)SFDR improvement using DEM (100 runs per point).
Figure 5.4:Simulation results of DEM performance when the first NDEMMSB are shuffled.
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1
(a)A conventional barrel shifter is implemented usingNDEM(2NDEM− 1) multiplexers.
(b)If a barrel shifter is used in a SAR CDAC some combinations are re-dundant. The number of multiplexer can be reduced.
Figure 5.5:The complexity of a barrel shifter can be reduced if it is used for a SAR CDAC with N inputs and 2N− 1 outputs. This figure shows an example for NDEM= 4.
5.4 Experimental Results 109 24µm
M ain SA R <0> M ain SA R <1>
Reference ADCBootstrapped Switches Input Buffers
240µm
100µm
CDACDEM
PRBS
LogicSAR
R-2.5R Ladder
Ref. Decap
BufferRef.
75µm
Figure 5.6: Chip micrograph and layout of 2×TI SAR ADC with reference ADC.
5.4 Experimental Results
A test chip has been fabricated in a 14 nm CMOS FinFET process. The total active area is 100×240 mm2, and 24×75 mm2is occupied by the ref-erence ADC as shown inFig. 5.6. At a conversion rate of 600 MS/s the total power consumption is 38.5 mW. The main ADC consumes 18.5 mW from a 0.85 V supply (VDD). The reference ADC runs at 200 MS/s and consumes 2.2 mW. The clock generation consumes 2.0 mW, including a CML-to-CMOS converter, a clock divider, clock buffers and bootstrap switches. The input buffers draw 15.8 mW from a 1 V supply (VDD,B).
Figure 5.7shows the measured INL of the reference ADC over 16 hard-ware samples. The INL of 10 out of 16 samples show little difference when DEM is enabled because the custom-designed MOM capacitors are well matched. This means that the unit capacitance can be decreased in fu-ture designs, thereby further reducing the input load of the reference ADC.
Smaller unit capacitance will also improve the speed of CDAC settling.
0.06 0.08 0.10 0.12 0.14 0.16
SigmaINL[LSB]
DEM disabled DEM enabled
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
Chip 0.25
0.30 0.35 0.40 0.45 0.50
max|INL|[LSB]
Figure 5.7:Standard deviation and maximum of INL over 16 mea-sured chips with DEM disabled or enabled.
−0.50
−0.25 0.00 0.25 0.50
INLChip2[LSB]
0 32 64 96 128 160 192 224 256
Code
−0.50
−0.25 0.00 0.25 0.50
INLChip13[LSB]
Figure 5.8:Comparison of INL with DEM disabled (solid) and en-abled (dashed).
5.4 Experimental Results 111
50 55 60
SNDR(Sinefit)[dB]
Background Calibration with HD3 Background Calibration
Foreground Calibration
65 70 75
HD3(FFT)[dB]
0 5 10 15 20 25 30 35 40
Iterations per channel [kSamples]
50 60 70
SFDR(FFT)[dB]
Figure 5.9: Settling behavior of background calibration compared with foreground calibration.
Figure 5.8plots INL of the measured Chip 2 and 13. The INL of Chip 13 shows that INL steps are reduced by enabling DEM. Steps in the INL is a results of capacitor mismatch. Chip 2 shows only little improvement in INL performance. However, as seen from the spiky shape of INL, the remaining INL errors stem mostly from incomplete CDAC settling. This can be solved by reducing the reference ADC speed and allowing longer settling times.
Figure 5.9compares the performance of a foreground and a background calibration with and without HD3 correction. Foreground calibration cor-rects gain mismatch with an on-chip programmable reference voltage and corrects offset mismatch in post-processing. The SNDR is calculated us-ing a sine-fit method, and the HD3and SFDR are calculated by averaging eight 1024-point FFTs. After 10,000 LMS iterations per channel, the back-ground calibration without HD3correction achieves the same median per-formance as the foreground calibration with 59.1 dB SNDR, 65.4 dB SFDR
2190 2195 2200
Offseta0[LSB] Channel 0Channel 1
0.0615 0.0620 0.0625
Gaina1
−2 · 10−7
−1 · 10−7 0
HD3a2
0 5 10 15 20 25 30 35 40
Iterations per channel [kSamples]
0 5 10
Error|e|[dB]
Figure 5.10:Settling of LMS algorithm.
and 65.4 dB HD3. After 30 kSamples, the background calibration with HD3
correction achieves a median SNDR of 60.1 dB, SFDR of 72.1 dB and HD3of 75.8 dB. Background calibration is performed in software post-processing with 14 bit precision. Reducing the precision of the calibration to 12 bit de-grades SNDR by only 0.2 dB and SFDR by 1 dB.
Figure 5.10shows the settling behavior of the LMS algorithm. Offset and gain calibration is settled after around 20 kSamples per channel. The HD3calibration is settled after 30 kSamples. The remaining error e after 30 kSamples is 0.65 LSBrms, corresponding to 43 dB SNR (matching SNR of reference ADC).
5.4 Experimental Results 113
45 50 55 60
SNDR(Sinefit)[dB]
VDD,B=1.0 V,VDD=0.85 V, fs=600 MS/s, Amp =0.7 Vpp,diff
0 50 100 150 200 250 300
Input Frequency [MHz]
45 50 55 60 65 70 75
SFDR(FFT)[dB]
Uncalibrated Reference ADC Foreground calibrated 2-tap, Offset, HD3 3-tap, Offset, HD3
Figure 5.11:SNDR and SFDR comparison of reference ADC, un-calibrated output, foreground-un-calibrated output (offset and gain calibrated at low frequency), and background-calibrated output.
Figure 5.11compares the SNDR and SFDR of the uncalibrated signal, reference signal, foreground-calibrated signal and background-calibrated signal with 2-tap or 3-tap filters. The uncalibrated main ADC is limited by 47 dB SFDR due to gain mismatch. Whereas, the reference ADC is noise limited, but it achieves high linearity with 73 dB SFDR. The ADC can be foreground calibrated by changing the full-scale voltages for the two chan-nels individually. Then, the foreground-calibrated signal is limited by HD3. Background calibration corrects offset and gain mismatch, as well as HD3. The SFDR of the background-calibrated signal matches SFDR of the ref-erence ADC. We can observe performance degradation when the input fre-quency approaches Nyquist. The 2-tap filter is unable to correct the phase mismatch for signals near Nyquist.
Figure 5.12shows the measured error plots, comparing the error signal e to the reference output Dref. Ideally, the error should have zero mean for all Dref. The variation around zero is the noise of the reference output. Fig-ure 5.12(a)shows that before calibration, the two channels have an offset and gain mismatch at 11 MHz input frequency. After calibration, the two channels align and the remaining error is the noise of the reference ADC.
At higher frequencies, the error plot shows a circular shape. This shape points to phase mismatch between the main ADC and the reference ADC.
The phase mismatch is due to the different bandwidths, because the ref-erence ADC has a much smaller sampling capacitance compared with the main ADC.Figure 5.12(b)shows that at Nyquist input using a 1-tap filter, a phase error remains after calibration. The LMS algorithm can still con-verge if the error has zero-mean, but this assumes some characteristic on the input signal that may not be fulfilled. Using a 3-tap filter the bandwidth mismatch and phase error can be corrected, as is evident fromFig. 5.12(c).
Figure 5.13compares the power spectra of the reference ADC and main ADC, before and after calibration. We see that the reference ADC is noise limited but has high linearity. The reference ADC achieves 43.6 dB SNDR and 72.8 dB SFDR with Nyquist input. The uncalibrated main output has a low noise-floor but has limited linearity. The SFDR is limited by gain mismatch to 47.3 dB.Figure 5.13(c)shows the power spectrum after offset, gain and HD3calibration. Bandwidth is corrected using a 3-tap filter. With a 3-tap filter, offset and HD3calibration, the ADC achieves 60.2 dB SNDR at Nyquist and an input amplitude of 0.7 Vpp,diff. The HD3is improved from 67.3 dB to 76.4 dB, and interleaving errors have been reduced by 23.7 dB.
Because of the frequency-dependency of the filter, the LMS algorithm has to be run for every frequency point. This is a realistic scenario in wire-less communications, where a baseband signal is upconverted to a carrier frequency. The background calibration has also been tested using a broad-band signal. This shows that the calibration algorithm does not assume any statistics of the input signal. A 25 MHz bandwidth QAM-16 around the cen-ter frequency fc= 250MHz is used.Figure 5.14shows the power spectra for uncalibrated and calibrated signals, with 1- and 3-tap filter. A 1-tap filter, which cannot correct bandwidth mismatch, is not able to fully correct gain mismatch with a broadband signal. The second harmonic distortion, which can be seen in the spectrum, originate from the single-ended signal source.
5.4 Experimental Results 115
−128 −64 0 64 128
ReferenceDref[LSB]
−10
ReferenceDref[LSB]
After Calibration Channel 0
Channel 1
(a) fin= 11MHz, 1-tap filter
−128 −64 0 64 128
ReferenceDref[LSB]
−10
ReferenceDref[LSB]
After Calibration Channel 0
Channel 1
(b) fin= 271MHz, 1-tap filter
−128 −64 0 64 128
ReferenceDref[LSB]
−10
ReferenceDref[LSB]
After Calibration Channel 0
Channel 1
(c)fin= 271MHz, 3-tap filter
Figure 5.12:Measured error plots shows the error signal e versus reference output Dref.
0 25 50 75 100 125 150
(a)Reference ADC output with2×downsampling.
0 50 100 150 200 250 300
(b)Uncalibrated main ADC output is limited by amplitude mismatch.
0 50 100 150 200 250 300
3-tap, Offset, HD3 NFFT= 16384
(c)Calibrated main ADC output with 3-tap filter, offset calibration, and HD3correction.
Figure 5.13:Power spectra with input near Nyquist (VDD,B= 1.0 V, VDD= 0.85 V, fs= 600 MS/s, Amp = 0.7 Vpp,diff, fin= 271 MHz).
5.5 Comparison with Prior Art 117
0 100 200 300 Frequency [MHz]
−60
−40
−20 0
PowerSpectrum[dBFS]
uncorrected
0 100 200 300 Frequency [MHz]
1-tap filter
0 100 200 300 Frequency [MHz]
3-tap filter
Gain Mismatch 2ndHarmonic (from source)
Figure 5.14:Measured power spectrum of a QAM-16 signal with 25 MHz bandwidth around fc= 250MHz.
5.5 Comparison with Prior Art
A 600 MS/s 60 dB SNDR 2×TI SAR ADC with background calibration using a noisy reference ADC was presented. Interleaving spurs due to offset, gain and bandwidth mismatch were reduced by 25 dB, and the third-order har-monic distortion was reduced by 10 dB. The −3 dB input bandwidth of the main ADC is 2 GHz with 50Ωtermination and ESD protection. The refer-ence ADC achieves 4 GHz input bandwidth. This architecture promises to be suitable as a gigasample converter if a moderately higher interleaving factor is applied. At higher input frequencies, calibration of timing skew becomes important to maintain the effective resolution. Timing-skew calibration can also be achieved with a reference ADC. Timing errors can be estimated us-ing a digital derivative filter [122] or based on the cross-correlation between the main and reference signal [123].
The reference ADC introduces a power overhead of 2.2 mW and has an area of 0.002 mm2. The reference ADC contributes 5 % to the total power
[122] Le Dortz et al., “A 1.62GS/s time-interleaved SAR ADC with digital background mismatch calibration achieving interleaving spurs below 70dBFS”, ISSCC, 2014.
[123] El-Chammas and Murmann, “A 12-GS/s 81-mW 5-bit time-interleaved flash ADC with background timing skew calibration”, JSSC, 2011.
consumption, although it runs at a conversion speed similar to that of a sub-ADC. The area and power-overhead diminishes when higher interleaving factors are used.
Table 5.2summarizes the ADC performance and compares it with recent TI ADCs that use a reference ADC for calibration. Chen and Murmann [118]
reuse the same sub-ADC as a reference running at the same speed. The sampling capacitance is reduced for extended bandwidth. This results in minimal design effort but the power consumption of the reference ADC is a significant portion of the overall power. Lin et al. [117] also reuse the sub-ADC, without any modification, but run it 6× slower. Liu and Chiu [116]
changed the architecture of the reference ADC to an algorithmic ADC from the main SAR ADC. The 9 bit algorithmic ADC runs 10× slower than a sub-ADC.
In contrast to all cited reference ADCs, the implemented reference ADC has a resolution that is 4 bit lower than the main ADC. This allows the reference ADC to be optimized for power and linearity, while allowing more random noise. This reference ADC can run at the same speed, while con-suming 3× less power than a sub-ADC. It has the highest energy efficiency compared with previously reported reference ADCs. Furthermore, the ref-erence ADC reuses as many blocks of the main SAR ADC as possible to minimize design effort.
In the presented work, gain and offset calibration converges after ap-proximately 20 kSamples per channel. This is the same number of samples per channel as in [116], which calibrates CDAC mismatch. But in this work the reference ADC runs 333× faster. The total time for calibrating the 2×TI ADC is
2 ·20,000Samples
200MS/s = 0.2ms
compared to 330 ms. Faster convergence time allows us to track faster vari-ations.
A similar calibration approach is known as “Split ADC” [124]. The idea is to split an ADC into two identical, half-sized ADCs. The two ADCs convert the same input independently, with different mismatch, and the average of the two outputs is the overall ADC output. Any difference between the two
[124] McNeill et al., “’Split ADC’ architecture for deterministic digital background calibration of a 16-bit 1-MS/s ADC”, JSSC, 2005.
5.5 Comparison with Prior Art 119
Table5.2:Performancesummaryandcomparison LiuLinChen ThisWorkISSCC09[115]VLSI16[117]A-SSCC16[118] TCAS-I12[116] Architecture10×8bitSAR4×10bitSAR4×8bitSAR2×12bitSAR ArchitectureRef9bitAlgorithmic10bitSAR8bitSAR8bitSAR Technology[nm]130166514 Supply[V]1.20.951.2/1.80.85/1.0 InputAmplitude[Vpp,diff]0.51.0–0.7 Conv.Rate[MS/s]60016001250600 Conv.RateRef[MS/s]0.664312.5200 SNDRatNyq.[dB]40.450.341at2.3GHz60.2 SNDRatNyq.Ref[dB]42.2at1.9MHz––43.6 SFDRatNyq.[dB]48.56161at2.3GHz72.6 SFDRatNyq.Ref[dB]61.4at1.9MHz–60at2.3GHz72.8 Power[mW]27.38.249.236.3 PowerRef[mW]3.01.619.22.2 FoMWalden[fJ/c.−st.]59022.959776.7 FoMSchreier[dB]140.4159.1140.6159.1 Area[mm2 ]1.10.0230.1170.024
outputs provides information to drive a calibration algorithm. The same concept has been simulated for an N×TI ADC using 2N +1 half-sized ADCs to correct interleaving errors [125]. Errors that are common to all sub-ADCs, e.g. harmonic distortion, cannot be calibrated using this method.
Alternatively, there exist calibration methods that are based on some statistical properties of the input signal. These properties are assumed to be known, e.g. mean, variance, or distribution. Correlation-based methods inject a known PRBS into the conversion. In the digital domain, the output can be correlated with the PRBS to gather information about the conver-sion, e.g. conversion gain. Statistical or correlation-based methods usually require a few million samples for the calibration to get sufficient data [121, 123,126]. This means that the convergence time of such methods can be several seconds.
[125] McNeill et al., “’Split ADC’ calibration for all-digital correction of time-interleaved ADC errors”, TCAS-II, 2009.
[126] Zhou et al., “A 12b 160MS/s synchronous two-step SAR ADC achieving 20.7 fJ/step FoM with opportunistic digital background calibration”, VLSI Circuits, 2014.
Chapter 6
Measurement of High-Speed ADCs
This chapter shows the measurement setup used to verify the performance of the ADC prototypes. It is largely based on [3] and has been added to this thesis for completeness.
High-speed high-resolution ADCs are challenging in design and also measurement. High accuracy on data and clock input have to be ensured.
To minimize non-linearity, it is important to avoid any signal-dependent errors. With these goals in mind, we discuss design tradeoffs that have to be considered for high-resolution ADCs. Furthermore, a full measurement setup using needle probing for high-speed ADCs is described.
On-chip memory enables accurate analysis of the output samples with-out the need for a high-speed digital interface or data decimation. An ef-ficient shift-register-based approach for an on-chip memory to handle the large aggregated output data of highly interleaved ADCs is presented. The shift-register-based custom memory is compared with a register-based syn-thesized memory in terms of area and energy efficiency.
6.1 Introduction
Figure 6.1 shows a block diagram of a typical ADC chip. The ADC core consists of an input buffer, a sampling circuit and a quantizer. The core takes the analog signal as the input and outputs a digital word of MRbits.
Its output is than stored in an on-chip memory, as shown here, or directly forwarded to a digital signal processor. It has four different power supply domains and a reference voltage. The clock signal is provided as a sine wave and then amplified to full-swing CMOS signals with the CML-to-CMOS converter.
[3] Kull and Luu, “Measurement of high-speed ADCs”, CICC, 2017.
121
Input Buffer Sampler Quantizer CML-to-CMOS
Converter
Memory (Shift register) MR
VDD,I VDD,C Vref VDD,A VDD,D
CKin Vin
VSS ADC Core
Figure 6.1:Block diagram of an ADC with on-chip memory.
A typical setup to measure a differential ADC is shown inFig. 6.2. It has two signal generators for the differential input signal INP/N and one signal generator including a balun to get the differential clock input CKP/N. Using 6 dB-splitters, the three signals are also connected to a sampling scope. The sampling scope is used to measure and calibrate the amplitude and phase matching of the input signal. The input common-mode Vcm,inand the clock common-mode Vcm,ckare set with bias-Ts. The differential input, differential clock, reference voltage and supply voltages are connected to the device under test (DUT). Using software analysis we can assess the performance of the ADC.
This chapter describes the main aspects of measuring high-speed ADCs [5, 127].Section 6.2focuses on the analog input, the clocking and the different configurations to provide a differential signal.Section 6.3explains the differ-ent power supplies and reference voltages.Section 6.4discusses remaining challenges, andSection 6.5describes an efficient and simple approach for an on-chip memory.
[5] Kull et al., “A 10b 1.5 GS/s pipelined-SAR ADC with background second-stage common-mode regulation and offset calibration in 14nm CMOS FinFET”, ISSCC, 2017.
[127] Kull et al., “A 90GS/s 8b 667mW 64×interleaved SAR ADC in 32nm digital SOI CMOS”, ISSCC, 2014.