6.5 ADC Output
6.5.1 Shift-Register On-Chip Memory
There are different approaches for on-chip memory. Digital synthesis is suit-able for building memory blocks based either on latches or static random access memory (SRAM). The former unfortunately results in a far inferior area efficiency, whereas the latter approach is much more complex and re-quires access to SRAM macros. SRAM is particularly beneficial for long capture sequences. An ADC output stream is sequential, thus no random access is necessary. This allows ADC memories be built from shift registers, which require only standard flip-flops (FFs) and have low complexity.
This section presents an FF-based shift-register memory that is very modular in its architecture. Its initial design effort is comparable to that of digital synthesis, but offers better scalability. Verification of a digital macro is generally more complete than analog simulations as used for the approach presented here. However, building a shift-register memory does not require any additional skills or tools than what is already needed to build an ADC.
The base cell for shift-register memories is the FF, which should be com-pact, reliable and fast. Different FFs can be used, starting from six tran-sistors per latch. We will not discuss the advantages and disadvantages of different latches, but present the standard eight-transistor inverting latch that is used in the FFs, seeFig. 6.3. This latch enables the sharing of drain and source of all transistors in layout, also if array-placed, which saves a significant amount of area. Optimizing the FF is key to a dense
shift-register-6.5 ADC Output 129
CK
CK
CK
CK
D Q
(a)Eight transistor inverting latch
CKCK D Q
LAT
CKCK D Q
LAT CK
CK
D Q
(b)Flip-flop consisting of two inverting latches Figure 6.3: Latch and FF that enable sharing of the drain and source of each transistor to save area.
based memory. The size of a custom-designed latch is still much larger than SRAM latches because of the special design rules used for SRAM that enable a much higher layout density, but require special process qualification.
The suggested length of the shift register is 4×2MRsamples [38], where MR is the resolution of the ADC. To simplify calibration on each channel in interleaved designs, it would be ideal to have 4 × 2MR samples for each sub-ADC. This is not necessary for assessing the full TI-ADC performance, however, it is still advisable to have a reasonable number of samples (on the order of 2MR) in order to enable per-channel analysis. In a recent design of a 8 bit 64×TI ADC, we save 256 samples per sub-ADC.
One approach to build a shift register is shown inFig. 6.4. A block of N1
FFs is clocked simultaneously. The clock signals have to be steep enough to prevent timing violations. If buffers are used between FFs, the last FFs in the chain have to be clocked first to avoid hold violations. A large number of clocks N2results in a long delay between the clock signal that goes into the shift register and the data capture, because the clock signal traverses 2×N2 [38] IEEE, “IEEE standard for terminology and test methods for analog-to-digital converters”, IEEE Std 1241-2010, 2011.
CK
Figure 6.4:A shift register with N1× N2FFs. Note that inverted clock signals are not shown.
inverters. This is no issue as long as the clock period is much longer than the worst-case delay of the total inverter chain. Nevertheless, this approach is quite power hungry because all FFs are clocked in each clock cycle. Splitting the shift register into several clock-gated domains shortens the delay and saves a lot of power.
Figure 6.5shows a clock-gated single-bit shift-register. It requires an additional address input that selects the internal block to which data is written to and read from. The bus length of the address is NA= log2N3. The counter for the address bits is shared among the bits that correspond to the same sub-ADC. As seen inFig. 6.6, a clock divider is used to clock the address counter. The division ratio can be between 1 and N3. The larger the ratio, the more power can be saved in the address logic, because the address bus lines and the counter states change less frequently. Note that the initial counter state does not need to be known for the shift register to function correctly and that this MR-bit shift register from Fig. 6.6is functionally equivalent to MR conventional 1 bit shift registers composed only of FFs (sharing a common clock). Both present the same interface: clock input CK, data input D, and data output Q. A large N3is desirable to save power on the shift register; a small N2assures high speed operation, and N1is sized reasonably large, but still small enough to prevent timing violations under
6.5 ADC Output 131 clock-gated blocks withN N3
Figure 6.5: One bit shift register with gated clocks and address input. Deco is used in each block to set its address.
CKD
ADDRGated SR(1bit) Q
CKD
ADDRGated SR(1bit) Q
CKD
ADDRGated SR(1bit) Q D1
Figure 6.6:Shift register (SR) for MRparallel bits with internal clock gating.
D1
InterleavedADC×IM SR-Memory×IM
t
Figure 6.7:Staggered data and clock signals from sub-ADCs of an interleaved design connect directly to the shift-register memory.
Slow serial interface connects the shift-register memory with off-chip equipment.
any circumstances. The best layout for this shift-register is a very long, but narrow shape to enable many shift registers to be placed in parallel.
Our implementation in a 14 nm CMOS FinFET process used N1= 16, N2= 2 and N3= 8. One 256 × 12 bit shift register consumes as little as 2 mW when clocked at 1 GHz and is fully functional up to 2 GHz. The area is approximately 1500 µm2.