Effect of nonidealities

Vertical Offsets in PD profile

In the process of reference buffering, the buffered reference edge will be ∆t away from the zero- crossing of the reference. The effect of a reference buffer edge delay or advance is shown in Fig. 5.20. 24. While the phase detector profile is still completely monotonic over ±π of oscillator phase as before, the profile is vertically asymmetric. This is not an issue, as long as the phase detector profile crosses zero, the loop will lock. In order to control ∆t, we include a reference buffer with tunable delay to ensure that the profile always crosses zero. It should be noted that setting the delay or advance of the buffered reference edge is a one time procedure to calibrate against process corner.

Delays in the T RACK sampling signal after the edge-selection process (ANDing of Sam- pleEDGE and V CO−,buf f) can cause the PD profile to be completely positive. The timing diagram

for this is shown in Fig. 5.21. This can be adjusted by advancing the reference buffer edge, so that combined with the T RACK path delay, the phase detector profile has a zero crossing.

Horizontal Offsets in PD profile

We have only talked of effects which cause the PD profile to move vertically up or down. All the while, the zero sample control voltage coincided with PLL phase error ∆φ = 0◦. The loop locks such that there is zero phase error between the sinewave at the sample switch source node and T RACK waveform at its gate. The matching resistance and bypass capacitance25_{at the reference}

pads introduce a phase shift between the crystal phase and the sinewave reference on-chip. There is also feedback path delay from the VCO to the T RACK signal. So the ideal locking phase error between crystal and LC-VCO is horizontally offset and is not zero.

24_{Advanced reference buffer edges can be generated using a complementary CMOS differential reference buffer}

discussed in Section 5.3

25

CHAPTER 5. LOW NOISE AND LOW SPUR RF PLL: REFERENCE-SAMPLING PLL 126

Figure 5.20: (a) When reference buffer generates an advanced edge with respect to reference sinewave zero-crossing, the PD resolves large VCO edge delays as advances. (b) Phase detec- tor profile remains monotonic with advanced reference buffer edge. (a) Delayed reference buffer edge resolves advances as delays (b) Phase detector profile with delayed reference buffer edge is also monotonic.

Figure 5.21: (a) Delay due to gates after T RACK is generated results in sampling due to DelayedT RACK. (b) Timing diagram when Ref Buf f is at t = 0. All samples are −ve and there is no steady state solution for the feedback loop. (c) By advancing Ref Buf f we can com- pensate for τdelay ensure a solution to the feedback loop.

CHAPTER 5. LOW NOISE AND LOW SPUR RF PLL: REFERENCE-SAMPLING PLL 128

SESCi component noise

The blocks after the AND gate, including the DFF do not add much noise as they operate on sharp edges. We have already discussed the effect of noise on the T RACK signal from the V CO buffer in each differential paths due the sampling and sample edge selection process.

Next, we discuss the effect of noise in the SESCi reference buffer on the PD profile. The SampleEDGE is generated by ANDing the VCO with the buffered reference (Ref Buf f ). The SampleEDGE is therefore defined either by the rising V CO+,buf f edge or the rising Ref Buf f .

The noise of Ref Buf f only interferes with the sample for PLL phase errors when V CO+,buf f is

near Ref Buf f . Fig. 5.22(a) shows the effect of buffer noise for a Ref Buf f advanced from the reference sinewave zero-crossing by |tadv| The reference buffer noise interferes with SampleEDGE

definiton for when desired rising V CO+,buf f edge (falling V CO−,buf f edge) is located at −tadv, and

when it is at −tadv+ 0.5TV CO. This introduces two zones of uncertainty, π/2 apart, in the phase

detector profile as shown in Fig. 5.22(b). By adjusting Ref Buf f advance or delay we can position the ideal locking point half way between these two zones. After lock is achieved, the FTL would prevent the loop from drifting too far off from this ideal locking point.

As long as noise of the reference buffer in SESCi does not overwhelm the π/2 zone, the noise performance at steady state can be robust. At lock, Ref Buf f and V CO_{+/−,buf f} track the reference sinewave with some additional error, that is their rising edge tracks the zero-crossing of the reference sinewave. So, the integrated jitter added by the reference buffer circuit should be about a tenth of 0.5Tvco, which with a 2.4 GHz VCO or TV CO = 416.7 ps. is about 21 ps. As this is not a very low

noise specification, the reference buffer design can be low power. 26

26

As V CO±,buf f and Ref Buf f both track the reference sinewave, we need to consider the sources of difference

between these two waveforms to estimate the effect of reference buffer noise on the PD profile.

We want V CO+,buf f to have the same jitter as V CO−,buf f so that the rising edge of the former in the sample

selection process identically matches the falling edge of the latter in the sampling process. This prevents a premature termination of the sampling process. At lock, they both have the same jitter at the LC-VCO output, equal to N2.XOnoiseplus some uncorrelated inverter buffer noise. We can assume the buffer in V CO+,buf f path is noiseless,

and refer all the inverter buffer error to V CO−,buf f. This means the noise on V CO+,buf f is just N2.XOnoise. The

noise on Ref Buf f is XOnoiseplus the noise of the reference buffer. The remaining N2.XOnoisenoise on V CO+,buf f

is not error, as it is what enables us to track V CO−,buf f identically. The uncertainty zone in PD profile is therefore

Figure 5.22: Effect of reference buffer noise on the PD profile creates two zones of uncertain samples π apart. The timing diagram is shown for noise on an advanced Ref Buf f edge. By tuning Ref Buf f position, we can position the zones of uncertainty for higher robustness and place the ideal locking point in the center of the range.

CHAPTER 5. LOW NOISE AND LOW SPUR RF PLL: REFERENCE-SAMPLING PLL 130