Sampled Phase detector (PD)

The phase error can be estimated in the voltage domain and the sampled phase detector (PD) shown in Fig. 5.12 is proposed. Here the VCO sinewave is converted to a square wave using the inverter buffer, and is used to sample the reference sinewave. A logic block, the Sample Edge Selection Circuit (SESCi), discussed later in 5.2.3, is used to select the relevant sample from the multiple values sampled onto the capacitor at each VCO edge. Broadly, the VCO edge near the

CHAPTER 5. LOW NOISE AND LOW SPUR RF PLL: REFERENCE-SAMPLING PLL 108

buffered reference edge is selected. As shown in the figure, the noise from the buffered reference inside the SESCi itself does not affect the value sampled on the clean sinewave reference.

PD profile

If there is a phase error ∆φ between the VCO and reference, the reference sinewave value sampled by the VCO edge near the buffered reference is

vP D = 2Arefsin(∆φ)/N (5.12)

vP D ≈ 2Aref∆φ/N for small phase errors (5.13)

Here, Aref is the amplitude of the reference sinewave, and the factor of 2 is from the differential

implementation discussed below.

This assumes that the buffered reference edge is itself close to the sinewave zero-crossing. The buffer circuit for satisfying these specifications is discussed in Section 5.3.

The phase detector profile is plotted in Fig. 5.13. Due to the virtual division by N, the proposed phase detector is monotonic over ±π of the VCO phase unlike SSPLL and ILCM which are only linear in ±π/2 of the VCO phase. As the profile is still not monotonic over the entire reference cycle (±π reference phase), an acquisition aid is still needed. The advantage of a very linear profile is that KP D is almost constant, and the noise performance is independent of the phase error at

lock, obviating the need for circuitry that ensures that the loop locks to the center of the lock range (verified in Fig. 5.33).

Differential implementation

Further, if the mismatch is low and the loop is Type-II, the static phase error will be close to zero. This means that the samples at lock will be close or equal to the zero crossing of the reference sinewave, and a differential implementation of the phase detector may be used to counter charge injection under steady state condition. A differential input reference is required and is generated from the single-ended crystal reference through an off-chip balun.

Figure 5.12: Proposed sampled phase detector and timing diagram. The VCO is used to evaluate phase error in the loop by sampling voltages on the reference sinewave. The relevant sample pertaining to the phase error is selected using the Sample Edge Selection Circuit (SESCi). The noise of SESCi does not affect the sampled value.

CHAPTER 5. LOW NOISE AND LOW SPUR RF PLL: REFERENCE-SAMPLING PLL 110

Figure 5.13: Profile of proposed sampled phase detector. The profile is montonic over ±πV CO

unlike ILCM and SSPD which are only monotonic over 0.5 ± πV CO

Half reference multiplexing

For the sampling phase, a large enough hold capacitance is required to hold the value for half the reference cycle 15. This is turn will translate to a larger sampling capacitance so that a larger portion of the sampled value moves from the sampling to the hold capacitance during the hold phase. In order to reduce the area, a multiplexing scheme at half the reference rate is proposed, as shown in Fig. 5.14. This avoids a large hold capacitance area.

In this scheme, a half rate 25 MHz signal is generated from the buffered reference (more on this in the SESCi). In each single-ended path, there are two sample capacitances which are muxed to the varactor control voltage. One sample capacitance tracks the signal every alternate reference cycle and presents its sampled value as the control voltage for one reference cycle period. The timing diagram is shown in Fig. 5.14. We discuss later the noise considerations that dictate the size of the sample capacitance. We have used 10 pF sample capacitance in this work, which is large enough to hold the sampled control voltage steady over 20 ns of the reference cycle.

15

Figure 5.14: Half rate multiplexing of samples in each differential path. This scheme reduces the area for sample and hold capacitances.

CHAPTER 5. LOW NOISE AND LOW SPUR RF PLL: REFERENCE-SAMPLING PLL 112

Timing Considerations

In the SSPD a very fast VCO sinewave is sampled for 0.5/fref time period by the reference square

wave. However, the RonCsamp time constant there had to be sufficiently smaller than 1/fV CO to

track the oscillator waveform closely and generate a voltage sample proportional to phase error. As SSPD uses a very small sampling capacitance, the switch size can be small, and the reference inverter buffer load remains small. This allows a fast buffering with less noise addition.

In the proposed PD, the sampling time is very small 0.5/fV CO which is N times lower than

the time available for sampling in the SSPD. However, the signal being sampled is N times slower as well. For 85% settling to a step response, RonCsamp need only be half the sampling time 16.

Compared to the V CO, the reference sinewave is slow enough that robust performance is obtained without needing a very large switch size to reduce RonCsamp. Even with a switch larger than

SSPLL, the power in the driving inverters operating at VCO frequency can be reduced by gating as discussed later in this chapter.