Fault Simulation

Due to the symmetry of the model, the short circuit fault is only simulated in Cable A1C2. To implement the faults with various locations in a handy way, Cable A1C2 is modeled as two segments of d and (200km-d) in length that connected in series, with an extra ‘Fault’ block set in between, as shown in Figure 3.6. The fault is configured as a permanent, solid (Rf=0) pole-to-pole fault occurring at t=1.0s, when the start-up transient has been faded away long before. Moreover, IGBTs will be blocked for self-protection when the cable current exceeds 13kA as indicated in [4].

Figure 3.6 System Overview after Fault Implementation

Extensive simulation work has been conducted, which produces a great amount of plots. Only the results of short circuit analysis at VSC_C2 during a fault which is 1km away from VSC_C2 (d=1km) is shwon here as in Figure 3.7. Compared to what is presented in Figure 3.2, the shapes for the measurements look alike. Plus,

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the currents flowing through the IGBTs (iIGBT1, iIGBT2 and iIGBT3) are also shown to illustrate the blocking of IGBTs during fault situations.

As can be observed from the figures, the insant when the capacitors are fully discharged (vDC=0, at the

start of 2nd stage), an abrupt overcurrent occurs in diodes, putting them at stake. In this specific case, the critical

time limit is 0.8ms and peak fault overcurrent is around 222kA. This justifies the necessity for DC protection. An

instictive idea will be either to isolate the fault within the critical time limit or to reduce the peak fault

overcurrent with fault current limiters. This validates the theory described in section 3.2 as put forward in [3, 17].

Figure 3.7 DC Cable Short Circuit Study of VSC_C2 (d=1km)

Afterward, DC cable short circuit faults with different distances to VSC_C2 (d) as 1km, 10km, 100km, 190km, 199km are simulated in Cable A1C2 (l= 200km) at t=1s. The results of DC voltage and DC current

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Chapter 3 DC Cable Short Circuit Study

detected at VSC_C2 in different sceniros are grouped in Matlab plots, as presented in Figure 3.8. It can be concluded that the closer the fault is to VSC_C2 station, the shorter the critical time and the larger the overcurrent magnitude, thus the more vulnerable the station and the cable connected to it will be. Besides, except for d=1 km or 10km, the DC voltage at VSC_C2 will not drop to 0. In this way, the most severe fault current overshoot is somewhat avoided. Actually, it can be further found out that no distinughishable ‘stages’ can be recognized from the complete fault response in these cases. On the other hand, the critical times for d=1km and 10km are 0.8ms and 2.2ms respectively. Also, when zooming in the fault current upon the fault moment, the travelling wave effect in DC current flowing out of VSC_C2 when d=1km and 10km can also be clearly observed in Figure 3.9, as the current is rising in a stepwise way.

(a)

(b)

Figure 3.8 (a) DC Voltage and (b) DC Current at VSC_C2 during Faults with Different Locations

Figure 3.9 Travelling Wave Effect in DC Current Detected in VSC_C2

1 1.01 1.02 1.03 1.04 1.05 0 100 200 300 400 time [s] D C Volt age [ k V]

DC Voltage with Different Distance to Fault

d=1km d=10km d=100km d=190km d=199km 0.980 1 1.02 1.04 1.06 1.08 1.1 20 40 60 80 100 120

Fault Current with Different Distance to Fault

time [s] D C C urre nt [ k A] d=1km d=10km d=100km d=190km d=199km 1 1 1.0001 1.0001 1.0002 1.0002 1.0003 0 20 40 60 80 100 120 time [s] D C C ure ent [ k A]

DC Current Travelling Wave

d=1km d=10km

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Apart from different fault locations, the impacts of various DC capacitance and fault impedance are also studied. Only the conclusion will be provided here: smaller DC capacitance or smaller fault impedance results in shorter critical time and larger overcurrent magnitude, which indicates a more severe situation.

3.5 Summary and Discussions

In this chapter, the DC cable short circuit fault study is illustrated in both theory and simulation. The conclusion indicates that the fault should be cleared before the critical time to protect the system from the

overcurrent. In other words, the key in DC cable short circuit fault protection is to isolate the fault before the

current exceeds the maximum current the components (such as the diodes) can sustain. This means that the DC faults have to be cleared within a few milliseconds, with fault detection, fault localization and fault isolation included [18]. However, such requirements cannot yet fully be satisfied by the existing technology [4, 16]. Therefore, more efficient and reliable fault detecting/locating methods have to be proposed, and fast fault isolation tools need to be designed and tested. Another possible solution is to limit either the magnitude or the derivative of the fault current to a reasonable range by introducing fault current limiters. As a result, the time constraint for the protection system becomes less strict. Each of the possibility will be explored in more details in the chapters to follow.

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