FIS-based Switching Command Transfers

When using Port Multipliers in a FIS-based switching fashion, the HBA has additional responsibilities to ensure high performance data transfers amongst multiple devices attached behind a single port.

5.6.5.2 Example

In the following example, the following occurs:

• System software places four commands in system memory for two separate devices: o Slot 0 contains a READ FPDMA QUEUED for PM port of 3 and NCQ tag of 0 o Slot 2 contains a WRITE DMA EXT for device with PM port of 7

o Slot 5 contains a READ DMA EXT for device with PM port of 7

o Slot 8 contains a WRITE FPDMA QUEUED for PM port of 3 and NCQ tag of 8 The prefetch bit in the command headers shall always be cleared to ‘0’ for FIS-based switching operation.

Following is a text description for the flow.

System Software Places four Commands in System Memory

Software builds a command into slot 8 as described in section 5.5.1. The command shall have a PRD table, is not ATAPI, has a WRITE FPDMA QUEUED opcode, has an NCQ tag of 8, and the PM port is set to 3. CH(8).W (Write) shall be set to ‘1’ and CH(8).P (Prefetch) shall be cleared to ‘0’. Software writes 100h to the PxSACT register. Software then writes 100h to the PxCI register.

Software builds a command into slot 5 as described in section 5.5.1. The command shall have a PRD table, is not ATAPI, has a READ DMA EXT opcode, and the PM port is set to 7. Both CH(5).W (Write) and CH(5).P (Prefetch) shall be cleared to ‘0’. Software writes 20h to the PxCI register. Software builds a command into slot 0 as described in section 5.5.1. The command shall have a PRD table, is not ATAPI, has a READ FPDMA QUEUED opcode, has an NCQ tag of 0, and the PM port is set to 3. CH(0).W (Write) shall be cleared to ‘0’, and CH(0).P (Prefetch) shall be cleared to ‘0’. Software writes 1h to the PxSACT register. Software then writes 1h to the PxCI register.

Software builds a command into slot 2 as described in section 5.5.1. The command shall have a PRD table, is not ATAPI, has a WRITE DMA EXT opcode, and the PM port is set to 7. CH(2).W (Write) shall be set to ‘1’ and CH(2).P (Prefetch) shall be cleared to ‘0’. Software writes 4h to the PxCI register.

At this point, the PxCI value is “00000125h” and the PxSACT register value is “00000101h” (bits 0 and 8 of PxSACT are set corresponding to the tags of the NCQ commands).

The HBA transmits Two Commands to the Device

The HBA may begin command sequences with either PM port 3 or PM port 7 first. The HBA shall maintain command ordering for each PM port, so the HBA may issue the command in slot 5 (for PM port 7) or slot 8 (for PM port 3). For this example, the HBA proceeds to issue the command in slot 8 first.

The HBA shall transfer the command from slot 8 to the device with PM port 3 traversing the macro states Exam:Fetch and Exam:Transmit. As this was a native queued command, the next FIS from the device with PM port 3 shall be a D2H Register FIS with the ‘I’ bit cleared to ‘0’.

The HBA shall then transfer the command for slot 5 to the device with PM port 7 traversing the macro states Exam:Fetch and Exam:Transmit. As this was a non-queued read command, the next FIS from the device with PM port 7 shall be a Data FIS.

D2H Register FIS arrives for PM port 3, slot 8

The command transferred to PM port 3 was an NCQ command, so the next FIS received from this device will be a D2H Register FIS. As a result of receiving the D2H Register FIS, the PxCI value is now “0000 0025h” since the DRQ, BSY, and ERR bits are cleared to zero.

The HBA then transfers the command from slot 0 to the device with PM port 3 traversing the macro states Exam:Fetch and Exam:Transmit. As this was a native queued command, the next FIS from the device with PM port 3 shall be a D2H Register FIS with the ‘I’ bit cleared to ‘0’.

Data Transfer for PM port 7, slot 5

The command issued to PM port 7 was a READ DMA EXT command, so the next FIS to receive is a Data FIS. When the Data FIS arrives, the HBA shall traverse the Exam:DMAReceive macro state. If the Data FIS did not satisfy the transfer count, another Data FIS shall be sent by the device and the HBA will again traverse the Exam:DMAReceive macro state. This process continues until the transfer count is satisfied. Note that FISes for other PM ports (port 3 in this case) may be interspersed between multiple Data FISes.

DMA Setup FIS arrives for PM port 3, slot 8

As this is a WRITE FPDMA QUEUED command, the next FIS from the device shall be a DMA Setup FIS. When this arrives, the HBA shall accept the FIS by traversing the Exam:AcceptNonData macro

If the Data FIS did not satisfy the transfer count, another DMA Activate FIS shall be sent from the device, and the HBA shall traverse the Exam:AcceptNonData and Exam:DMATransmit macro states again to send another Data FIS. This process continues until the transfer count is satisfied. Note that FISes for other PM ports (port 7 in this case) may be interspersed between multiple Data FISes.

D2H Register FIS arrives for PM port 3, slot 0

The command transferred to PM port 3 was an NCQ command, so the next FIS received from this device will be a D2H Register FIS. As a result of receiving the D2H Register FIS, the PxCI value is now “0000 0024h” since the DRQ, BSY, and ERR bits are cleared to zero.

D2H Register FIS arrives for PM port 7, slot 5

The command transferred to PM port 7 was a READ DMA EXT, so the next D2H Register FIS received from this device will complete the transfer and update PxCI. The PxCI value is now “0000 0004h” since DRQ, BSY, and ERR bits are cleared to zero.

The HBA is now free to transfer the next command for port 7, which is located in slot 2.

SDB FIS arrives for PM port 3, slot 8

As a result of receiving the SDB FIS, the PxSACT value is now “0000 0001h”.

The HBA transmits One Command to the Device

The HBA may now begin the command sequence for PM port 7.

The HBA shall then transfer the command for slot 2 to the device with PM port 7 traversing the macro states Exam:Fetch and Exam:Transmit. As this was a non-queued write command, the next FIS from the device with PM port 7 shall be a DMA Activate FIS.

Data Transfer for PM port 7, slot 2

As this was a WRITE DMA EXT command, the response from the device shall be a DMA Activate FIS. When this arrives, the HBA shall accept the FIS by traversing the Exam:AcceptNonData macro state, and shall send a Data FIS by traversing the Exam:DMATransmit macro state.

If the Data FIS did not satisfy the transfer count, another DMA Activate FIS shall be sent from the device, and the HBA shall traverse the Exam:AcceptNonData and Exam:DMATransmit macro states again to send another Data FIS. This process continues until the transfer count is satisfied. When the Data FIS that completes the transfer count finishes, the next FIS from the device shall be a D2H Register FIS.

D2H Register FIS arrives for PM port 7, slot 2

The command transferred to PM port 7 was a WRITE DMA EXT, so the next D2H Register FIS received from this device will complete the transfer and update PxCI. The PxCI value is now “0000 0000h” since DRQ, BSY, and ERR bits are cleared to zero.

The HBA shall accept this FIS by traversing the Exam:AcceptNonData macro state, and then traverses the Exam:DMASetup macro state to process the DMA Setup FIS. As this was a READ FPDMA QUEUED command, the next FIS from the device shall be a Data FIS.

Data Transfer for PM port 3, slot 0

As this was a READ FPDMA QUEUED command, the next FIS from the device shall be a Data FIS. When this arrives, the HBA shall traverse the Exam:DMAReceive macro state.

If the Data FIS did not satisfy the transfer count, another Data FIS shall be sent from the device, and the HBA shall traverse the Exam:DMAReceive macro states again. This process continues until the transfer count is satisfied.

SDB FIS arrives for PM port 3, slot 8

6 Error Reporting and Recovery

All errors within an HBA occur within ports. There are no errors that apply to the entire host controller. There are several sources of errors that could occur during a transfer. Examples of errors are:

• System Memory – Bad system memory pointers cause data fetches and stores to be lost • Interface / Device - such as CRC problems, illegal state machine transitions, etc.