Native Queued Command Transfers - Transfer Examples (Informative)

5.6 Transfer Examples (Informative)

5.6.4 Native Queued Command Transfers

The ATA/ATAPI-7 queued feature set is not supported by AHCI (including the READ QUEUED (EXT), WRITE QUEUED (EXT), and SERVICE commands). Queued operations are supported in AHCI using the READ FPDMA QUEUED and WRITE FPDMA QUEUED commands when the HBA and device support native command queuing.

To allow a simple mechanism for the HBA to map command list slots to queue entries, software must match the tag number it uses to the slot it is placing the command in. For example, if a queued command is placed in slot 5, the tag for that command must be 5.

System software must determine the maximum tag allowed by the device and the HBA and it must use the lower bound of the two. For example, if the HBA has 8 entries in its command list, and the SATA device only has 4, only tags 0 – 3 in the device may be used, and only command list entries 0 – 3 may be used in the HBA.

Data transfers are activated with the flow described below via the DMA Setup FIS, and command completion is performed via the Set Device Bits FIS.

5.6.4.2 Example

In the following example, the following occurs:

• System software places 4 commands in system memory: o Slot 0 contains a READ FPDMA QUEUED o Slot 2 contains a WRITE FPDMA QUEUED o Slot 5 contains a READ FPDMA QUEUED o Slot 8 contains a WRITE FPDMA QUEUED

• The HBA fetches the first 3 commands, transfers them to the device, and receives a successful completion.

• Before the HBA can send the 4th command to the device, the device sends a DMA Setup FIS to transfer data for the command in slot 2.

• A data transfer occurs to slot 2. • The HBA transfers slot 8 to the device. • A data transfer occurs to slot 5.

• The device sends an SDB FIS to clear slots 2 and 5. • A data transfer occurs to slot 8.

• The device sends an SDB FIS to clear slot 8. • A data transfer occurs to slot 0.

Other items to note in this data flow:

• In both WRITE FPDMA QUEUED commands, the auto-activate bit is not set in the FIS. • Every SDB FIS received has the ‘I’ bit set to ‘1’.

Following is a text description for the flow.

System Software Places 4 Commands in System Memory

Software builds a command into slot 0 as described in section 5.5.1. The command shall have a PRD table, is not ATAPI, and has a READ FPDMA QUEUED opcode. CH(0).W (Write) shall be cleared to ‘0’, and CH(0).P (Prefetch) shall be cleared to ‘0’.

Software builds a command into slot 2 as described in section 5.5.1. The command shall have a PRD table, is not ATAPI, and has a WRITE FPDMA QUEUED opcode. CH(2).W (Write) shall be set to ‘1’ and CH(2).P (Prefetch) shall be cleared to ‘0’.

Software builds a command into slot 5 as described in section 5.5.1. The command shall have a PRD table, is not ATAPI, and has a READ FPDMA QUEUED opcode. Both CH(5).W (Write) and CH(5).P (Prefetch) shall be cleared to ‘0’.

Software builds a command into slot 8 as described in section 5.5.1. The command shall have a PRD table, is not ATAPI, and has a WRITE FPDMA QUEUED opcode. CH(8).W (Write) shall be set to ‘1’, and CH(8).P (Prefetch) shall be cleared to ‘0’.

At this point, the PxCI and PxSACT register values are “00000125h” (bits 0, 2, 5, and 8 are set). The HBA transmits the First 3 Commands to the Device

The HBA shall transfer the command from slot 0 to the device traversing the macro states Exam:Fetch and Exam:Transmit. As this was a native queued command, the next FIS from the device shall be a D2H Register FIS with the ‘I’ bit cleared to ‘0’.

The HBA shall accept this FIS by traversing the Exam:AcceptNonData macro state. The ‘I’ bit was cleared to ‘0’ so the HBA shall traverse the Exam:D2HNoIntr state. PxCI is now equal to “00000124h”.

The HBA shall transfer the command from slot 2 to the device traversing the macro states Exam:Fetch and Exam:Transmit. As this was a native queued command, the next FIS from the device shall be a D2H Register FIS with the ‘I’ bit cleared to ‘0’.

The HBA shall transfer the command from slot 5 to the device traversing the macro states Exam:Fetch and Exam:Transmit. As this was a native queued command, the next FIS from the device shall be a D2H Register FIS with the ‘I’ bit cleared to ‘0’.

DMA Setup FIS Arrives for slot 2

The HBA is now in an idle state, but before it can fetch a new command, a short FIS arrives from the device. This FIS is the DMA Setup FIS. The HBA shall accept this FIS by traversing the Exam:AcceptNonData macro state, and then traverses the Exam:DMASetup macro state to process the DMA Setup FIS. The tag indicated in the FIS was for slot 2.

Data Transfer for slot 2

As this was a DMA write command, and the auto-activate bit was not set in the FIS, the next FIS from the device shall be a DMA Activate FIS. When this arrives, the HBA shall accept the FIS by

traversing the Exam:AcceptNonData macro state, and shall send a Data FIS by traversing the Exam:DMATransmit macro state.

If the Data FIS did not satisfy the transfer count, another DMA Activate FIS shall be sent from the device, and the HBA shall traverse the Exam:AcceptNonData and Exam:DMATransmit macro states again to send another Data FIS. This process continues until the transfer count is satisfied. The state machine is now in P:Idle

HBA transfers slot 8 to the device

Since PxCI is not all 0h, and no other FIS is coming in from the device, the HBA shall transfer the command from slot 8 to the device traversing the macro states Exam:Fetch and Exam:Transmit. As this was a native queued command, the next FIS from the device shall be a D2H Register FIS with the ‘I’ bit cleared to ‘0’.

Data transfer to slot 5

A short FIS arrives from the device of type DMA Setup FIS. The HBA shall accept this FIS by traversing the Exam:AcceptNonData macro state, and then traverses the Exam:DMASetup macro state to process the DMA Setup FIS. The tag indicated in the FIS was for slot 5.

As this was a DMA read command, the next FIS from the device shall be a Data FIS. When this arrives, the HBA shall traverse the Exam:DMAReceive macro state.

If the Data FIS did not satisfy the transfer count, another Data FIS shall be sent from the device, and the HBA shall traverse the Exam:DMAReceive macro states again. This process continues until the transfer count is satisfied. The HBA state machine is now in P:Idle.

Device sends SDB FIS to clear slots 2 and 5

At this point, the device sends an SDB FIS to indicate slots 2 and 5 are complete. The HBA shall accept this FIS by traversing the Exam:AcceptNonData macro state, and then traverses the SDB:Entry, and, since the received FIS had the ‘I’ bit set, the SDB:SetIntr [ SDB:SetIS [ SDB:GenIntr states, and returns to PM:Aggr [ P:Idle. The PxSACT register is now equal to “00000101h”.

Data transfer occurs to slot 8

As this was a DMA write command, and the auto-activate bit was not set in the FIS, the next FIS from the device shall be a DMA Activate FIS. When this arrives, the HBA shall accept the FIS by traversing the Exam:AcceptNonData macro state, and shall send a Data FIS by traversing the Exam:DMATransmit macro state.

Device sends SDB FIS to clear slot 8

At this point, the device sends an SDB FIS to indicate slot 8 is complete. The HBA shall accept this FIS by traversing the Exam:AcceptNonData macro state, and then traverses the SDB:Entry, and, since the received FIS had the ‘I’ bit set, the SDB:SetIntr [ SDB:SetIS [ SDB:GenIntr states, and returns to PM:Aggr [ P:Idle. The PxSACT register is now equal to “00000001h”.

As this was a DMA read command, the next FIS from the device shall be a Data FIS. When this arrives, the HBA shall traverse the Exam:DMAReceive macro state.

Device sends SDB FIS to clear slot 0

At this point, the device sends an SDB FIS to indicate slot 0 is complete. The HBA shall accept this FIS by traversing the Exam:AcceptNonData macro state, and then traverses the SDB:Entry, and, since the received FIS had its I bit set, the SDB:SetIntr [ SDB:SetIS [ SDB:GenIntr states, and returns to PM:Aggr. The PxSACT register is now equal to “00000000h”.

Since the PxCI and PxSACT registers are now both equal to “00000000h”, if the HBA was enabled for aggressive power management, the HBA shall first request the link to be placed in either the Partial or Slumber power management after the PM:Aggr state.

5.6.4.3 NCQ Unload (Informative)

When using Native Command Queuing in a laptop environment, the host needs to be able to park the head due to excessive movement (e.g. the laptop being dropped). The IDLE IMMEDIATE command with the Unload Feature as defined in ATA/ATAPI-7 clause 6.20 instructs the device to park its head and stop processing any outstanding commands. This command may be issued while FPDMA READ QUEUED and FPDMA WRITE QUEUED commands are outstanding on the host. For more information on IDLE IMMEDIATE with the Unload Feature please reference SATA 2.6 or ATA/ATAPI-7.

5.6.5 FIS-based Switching Command Transfers

In document Serial ATA AHCI 1.3 Specification (Page 79-82)