Format: (qp) ldffsz.fldtype.ldhint f1 = [r3] no_base_update_form M9 (qp) ldffsz.fldtype.ldhint f1 = [r3], r2 reg_base_update_form M7 (qp) ldffsz.fldtype.ldhint f1 = [r3], imm9 imm_base_update_form M8 (qp) ldf8.fldtype.ldhint f1 = [r3] integer_form, no_base_update_form M9 (qp) ldf8.fldtype.ldhint f1 = [r3], r2 integer_form, reg_base_update_form M7 (qp) ldf8.fldtype.ldhint f1 = [r3], imm9 integer_form, imm_base_update_form M8
(qp) ldf.fill.ldhint f1 = [r3] fill_form, no_base_update_form M9
(qp) ldf.fill.ldhint f1 = [r3], r2 fill_form, reg_base_update_form M7 (qp) ldf.fill.ldhint f1 = [r3], imm9 fill_form, imm_base_update_form M8 Description: A value consisting of fsz bytes is read from memory starting at the address specified by
the value in GR r3. The value is then converted into the floating-point register format
and placed in FR f1. See Section 5.1, “Data Types and Formats” on page 1:85 for details
on conversion to floating-point register format. The values of the fsz completer are given in Table 2-35. The fldtype completer specifies special load operations, which are described in Table 2-36.
For the integer_form, an 8-byte value is loaded and placed in the significand field of FR
f1 without conversion. The exponent field of FR f1 is set to the biased exponent for 2.063
(0x1003E) and the sign field of FR f1 is set to positive (0).
For the fill_form, a 16-byte value is loaded, and the appropriate fields are placed in FR
f1 without conversion. This instruction is used for reloading a spilled register. See
Section 4.4.4, “Control Speculation” on page 1:60 for details.
In the base update forms, the value in GR r3 is added to either a signed immediate
value (imm9) or a value from GR r2, and the result is placed back in GR r3. This base
register update is done after the load, and does not affect the load address. In the reg_base_update_form, if the NaT bit corresponding to GR r2 is set, then the NaT bit
corresponding to GR r3 is set and no fault is raised.
Table 2-35. fsz Completers
fsz Completer Bytes Accessed Memory Format
s 4 bytes Single precision
d 8 bytes Double precision
e 10 bytes Extended precision
Table 2-36. FP Load Types
fldtype
Completer Interpretation Special Load Operation
none Normal load
s Speculative load Certain exceptions may be deferred rather than generating a fault. Deferral causes NaTVal to be placed in the target register. The NaTVal value is later used to detect deferral.
a Advanced load An entry is added to the ALAT. This allows later instructions to check for colliding stores. If the referenced data page has a non-speculative attribute, no ALAT entry is added to the ALAT and the target register is set as follows: for the integer_form, the exponent is set to 0x1003E and the sign and significand are set to zero; for all other forms, the sign, exponent and significand are set to zero. The absence of an ALAT entry is later used to detect deferral or collision.
ldf
For more details on speculative, advanced and check loads see Section 4.4.4, “Control Speculation” on page 1:60 and Section 4.4.5, “Data Speculation” on page 1:63. Details on memory attributes are described in Section 4.4, “Memory Attributes” on page 2:75. For the non-speculative load types, if NaT bit associated with GR r3 is 1, a Register NaT
Consumption fault is taken. For speculative and speculative advanced loads, no fault is raised, and the exception is deferred. For the base-update calculation, if the NaT bit associated with GR r2 is 1, the NaT bit associated with GR r3 is set to 1 and no fault is
raised.
The value of the ldhint modifier specifies the locality of the memory access. The mnemonic values of ldhint are given in Table 2-34 on page 3:152. A prefetch hint is implied in the base update forms. The address specified by the value in GR r3 after the
base update acts as a hint to prefetch the indicated cache line. This prefetch uses the locality hints specified by ldhint. Prefetch and locality hints do not affect program functionality and may be ignored by the implementation. See Section 4.4.6, “Memory Hierarchy Control and Consistency” on page 1:69 for details.
In the no_base_update form, the value in GR r3 is not modified and no prefetch hint is implied.
The PSR.mfl and PSR.mfh bits are updated to reflect the modification of FR f1.
Hardware support for ldfe (10-byte) instructions that reference a page that is neither a cacheable page with write-back policy nor a NaTPage is optional. On processor models that do not support such ldfe accesses, an Unsupported Data Reference fault is raised when an unsupported reference is attempted. The fault is delivered only on the normal, advanced, and check load flavors. Control-speculative flavors of ldfe always defer the Unsupported Data Reference fault.
sa Speculative Advanced load
An entry is added to the ALAT, and certain exceptions may be deferred. Deferral causes NaTVal to be placed in the target register, and the processor ensures that no ALAT entry exists for the target register. The absence of an ALAT entry is later used to detect deferral or collision. c.nc Check load –
no clear
The ALAT is searched for a matching entry. If found, no load is done and the target register is unchanged. Regardless of ALAT hit or miss, base register updates are performed, if specified. An implementation may optionally cause the ALAT lookup to fail independent of whether an ALAT entry matches. If not found, a load is performed, and an entry is added to the ALAT (unless the referenced data page has a
non-speculative attribute, in which case no ALAT entry is allocated). c.clr Check load – clear The ALAT is searched for a matching entry. If found, the entry is
removed, no load is done and the target register is unchanged. Regardless of ALAT hit or miss, base register updates are performed, if specified. An implementation may optionally cause the ALAT lookup to fail independent of whether an ALAT entry matches. If not found, a clear check load behaves like a normal load.
Table 2-36. FP Load Types (Continued)
fldtype
Operation: if (PR[qp]) {
size = (fill_form ? 16 : (integer_form ? 8 : fsz)); speculative = (fldtype == ‘s’ || fldtype == ‘sa’); advanced = (fldtype == ‘a’ || fldtype == ‘sa’); check_clear = (fldtype == ‘c.clr’ );
check_no_clear = (fldtype == ‘c.nc’); check = check_clear || check_no_clear; translate_address = 1;
read_memory = 1; itype = READ;
if (speculative) itype |= SPEC; if (advanced) itype |= ADVANCE; if (size == 10) itype |= UNCACHE_OPT;
if (reg_base_update_form || imm_base_update_form) check_target_register(r3);
fp_check_target_register(f1);
if (tmp_isrcode = fp_reg_disabled(f1, 0, 0, 0)) disabled_fp_register_fault(tmp_isrcode, itype);
if (!speculative && GR[r3].nat) // fault on NaT address
register_nat_consumption_fault(itype);
defer = speculative && (GR[r3].nat || PSR.ed);// defer exception if spec if (check && alat_cmp(FLOAT, f1)) {
translate_address = alat_translate_address_on_hit(fldtype, FLOAT, f1);
read_memory = alat_read_memory_on_hit(fldtype, FLOAT, f1); }
if (!translate_address) {
if (check_clear || advanced) // remove any old ALAT entry
alat_inval_single_entry(FLOAT, f1);
} else {
if (!defer) {
paddr = tlb_translate(GR[r3], size, itype, PSR.cpl, &mattr, &defer);
spontaneous_deferral(paddr, size, UM.be, mattr, UNORDERED,
ldhint, &defer);
if (!defer && read_memory)
val = mem_read(paddr, size, UM.be, mattr, UNORDERED, ldhint); }
if (check_clear || advanced) // remove any old ALAT entry
alat_inval_single_entry(FLOAT, f1); if (speculative && defer) {
FR[f1] = NATVAL;
} else if (advanced && !speculative && defer) { FR[f1] = (integer_form ? FP_INT_ZERO : FP_ZERO);
} else { // execute load normally
FR[f1] = fp_mem_to_fr_format(val, size, integer_form);
if ((check_no_clear || advanced) && ma_is_speculative(mattr)) // add entry to ALAT alat_write(fldtype, FLOAT, f1, paddr, size);
ldf
}
if (imm_base_update_form) { // update base register
GR[r3] = GR[r3] + sign_ext(imm9, 9);
GR[r3].nat = GR[r3].nat;
} else if (reg_base_update_form) { GR[r3] = GR[r3] + GR[r2];
GR[r3].nat = GR[r3].nat || GR[r2].nat;
}
if ((reg_base_update_form || imm_base_update_form) && !GR[r3].nat) mem_implicit_prefetch(GR[r3], ldhint, itype);
fp_update_psr(f1);
}
Interruptions: Illegal Operation fault Data NaT Page Consumption fault Disabled Floating-point Register fault Data Key Miss fault
Register NaT Consumption fault Data Key Permission fault
Unimplemented Data Address fault Data Access Rights fault
Data Nested TLB fault Data Access Bit fault
Alternate Data TLB fault Data Debug fault
VHPT Data fault Unaligned Data Reference fault
Data TLB fault Unsupported Data Reference fault