lfetch — Line Prefetch
Format: (qp) lfetch.lftype.lfhint [r3] no_base_update_form M18
(qp) lfetch.lftype.lfhint [r3], r2 reg_base_update_form M20
(qp) lfetch.lftype.lfhint [r3], imm9 imm_base_update_form M22
(qp) lfetch.lftype.excl.lfhint [r3] no_base_update_form, exclusive_form M18 (qp) lfetch.lftype.excl.lfhint [r3], r2 reg_base_update_form, exclusive_form M20 (qp) lfetch.lftype.excl.lfhint [r3], imm9 imm_base_update_form, exclusive_form M22 Description: The line containing the address specified by the value in GR r3 is moved to the highest
level of the data memory hierarchy. The value of the lfhint modifier specifies the locality of the memory access; see Section 4.4, “Memory Access Instructions” on page 1:57 for
details. The mnemonic values of lfhint are given in Table 2-38.
The behavior of the memory read is also determined by the memory attribute associated with the accessed page. See Chapter 4, “Addressing and Protection” in Volume 2. Line size is implementation dependent but must be a power of two greater than or equal to 32 bytes. In the exclusive form, the cache line is allowed to be marked in an exclusive state. This qualifier is used when the program expects soon to modify a location in that line. If the memory attribute for the page containing the line is not cacheable, then no reference is made.
The completer, lftype, specifies whether or not the instruction raises faults normally
associated with a regular load. Table 2-37 defines these two options.
In the base update forms, after being used to address memory, the value in GR r3 is
incremented by either the sign-extended value in imm9 (in the imm_base_update_form)
or the value in GR r2 (in the reg_base_update_form). In the reg_base_update_form, if
the NaT bit corresponding to GR r2 is set, then the NaT bit corresponding to GR r3 is set
– no fault is raised.
In the reg_base_update_form and the imm_base_update_form, if the NaT bit corresponding to GR r3 is clear, then the address specified by the value in GR r3 after
the post-increment acts as a hint to implicitly prefetch the indicated cache line. This implicit prefetch uses the locality hints specified by lfhint. The implicit prefetch does not affect program functionality, does not raise any faults, and may be ignored by the implementation.
In the no_base_update_form, the value in GR r3 is not modified and no implicit prefetch hint is implied.
If the NaT bit corresponding to GR r3 is set then the state of memory is not affected. In
the reg_base_update_form and imm_base_update_form, the post increment of GR r3 is performed and prefetch is hinted as described above.
lfetch instructions, like hardware prefetches, are not orderable operations, i.e., they have no order with respect to prior or subsequent memory operations.
Table 2-37. lftype Mnemonic Values
lftype Mnemonic Interpretation
none No faults are raised fault Raise faults
A faulting lfetch to an unimplemented address results in an Unimplemented Data Address fault. A non-faulting lfetch to an unimplemented address does not take the fault and will not issue a prefetch request, but, if specified, will perform a register post-increment.
Both the non-faulting and the faulting forms of lfetch can be used speculatively. The purpose of raising faults on the faulting form is to allow the operating system to resolve problems with the address to the extent that it can do so relatively quickly. If problems with the address cannot be resolved quickly, the OS simply returns to the program, and forces the data prefetch to be skipped over.
Specifically, if a faulting lfetch takes any of the listed faults (other than Illegal Operation fault), the operating system must handle this fault to the extent that it can do so relatively quickly and invisibly to the interrupted program. If the fault cannot be handled quickly or cannot be handled invisibly (e.g., if handling the fault would involve terminating the program), the OS must return to the interrupted program, skipping over the data prefetch. This can easily be done by setting the IPSR.ed bit to 1 before executing an rfi to go back to the process, which will allow the lfetch.fault to perform its base register post-increment (if specified), but will suppress any prefetch request and hence any prefetch-related fault. Note that the OS can easily identify that a faulting lfetch was the cause of the fault by observing that ISR.na is 1, and
ISR.code{3:0} is 4. The one exception to this is the Illegal Operation fault, which can be caused by an lfetch.fault if base register post-increment is specified, and the base register is outside of the current stack frame, or is GR0. Since this one fault is not related to the prefetch aspect of lfetch.fault, but rather to the base update portion, Illegal Operation faults on lfetch.fault should be handled the same as for any other instruction.
Table 2-38. lfhint Mnemonic Values
lfhint Mnemonic Interpretation
none Temporal locality, level 1 nt1 No temporal locality, level 1 nt2 No temporal locality, level 2 nta No temporal locality, all levels
lfetch
Operation: if (PR[qp]) {
itype = READ|NON_ACCESS;
itype |= (lftype == ‘fault’) ? LFETCH_FAULT : LFETCH; if (reg_base_update_form || imm_base_update_form)
check_target_register(r3);
if (lftype == ‘fault’) { // faulting form
if (GR[r3].nat && !PSR.ed) // fault on NaT address register_nat_consumption_fault(itype);
}
excl_hint = (exclusive_form) ? EXCLUSIVE : 0;
if (!GR[r3].nat && !PSR.ed) {// faulting form already faulted if r3 is nat paddr = tlb_translate(GR[r3], 1, itype, PSR.cpl, &mattr, &defer);
if (!defer)
mem_promote(paddr, mattr, lfhint | excl_hint); } if (imm_base_update_form) { GR[r3] = GR[r3] + sign_ext(imm9, 9); GR[r3].nat = GR[r3].nat; } else if (reg_base_update_form) { GR[r3] = GR[r3] + GR[r2];
GR[r3].nat = GR[r2].nat || GR[r3].nat;
}
if ((reg_base_update_form || imm_base_update_form) && !GR[r3].nat) mem_implicit_prefetch(GR[r3], lfhint | excl_hint, itype);
}
Interruptions: Illegal Operation fault Data Page Not Present fault
Register NaT Consumption fault Data NaT Page Consumption fault
Unimplemented Data Address fault Data Key Miss fault
Data Nested TLB fault Data Key Permission fault
Alternate Data TLB fault Data Access Rights fault
VHPT Data fault Data Access Bit fault