Quartus Prime Lite Edition 17.1 has been used to compile the designs for emula- tion on a DE0-Nano development board. This board contains a Cyclone IV FPGA, and is shown in Fig.5.17. The design passed the timing analysis of Quartus and was latch-free. After compilation, Quartus was used to program the board, along with the contents of the Main Memory. This is provided by reading the contents of an ihex
file, named dm system memory xxxxx.hex. The LEDs are used during tests on the development board to provide feedback. Just like the simulations, the Dependability Manager processor is instantiated in a wrapper entity, but this time with a clock di- vider process. This process is added to reduce the 50 MHz clock frequency of the DE0-Nano to other lower frequencies. It was unnecessary since the timing analysis
Figure 6.5: Setup used to gather emulation test.
Figure 6.6: Data gathered with logic analyser.
was successful. The wrapper entity has a clock input, two inputs for buttons and 8 output ’pins’ for the LEDs. Later on, the GPIO header was also included and the TAP connections have been mapped to it. A test setup was created by connecting a logic analyser to the GPIO header of the DE0-Nano. A waveform was created with the logic analyser, see Fig. 6.6. The example from Table 6.2 was continuously ran on the Mingle network. The wrapper entity of the emulation also contains one of the IJTAG network entities to communicate with the retargeting engine or with the interrupt management unit. This was, off-course, based on which test was executed.
The compilation results of Quartus are shown in Table 6.8. It shows the different design entities of the dependability manager along with their respective resource us- age. The resources are expressed as Logic Cells (LC), Dedicated Logic Registers (DLR) and Memory Bits. The basic building block of Altera FPGAs are Logic Ele- ments. They can be configured in normal mode or arithmetic mode. The memory bits can be used with the Altera Memory IP. The LC and DLR are probably related to the modes of the logic elements but no more information given about them [82]. The FPGA was an Altera Cyclone IV EP4CE22F17C6N; it contains 22000 logic ele-
Table 6.8: FPGA resource usage of Dependability Manager in Quartus.
Entity LC DLR Memory Bits
fpga dm main 12.556 3.722 294.912
dm main processor:unit under test 12.283 3.502 294.912
dm main control:control 393 129 -
dm system bus master:memory manager 809 177 -
dm main registers:registers 2.179 1.056 -
dm main alu:alu 645 33 -
dm main alu in mux:b mux 677 0 -
dm system bus slave:slave ram memory 198 76 262.144
dm system bus leds:slave leds 17 12 -
dm retargeting engine:retargeting engine 6.790 1.352 32.768
dm main interrupt manager:interrupt manager 811 612 -
dm tap control:ijtag tap control 42 21 -
Mingle:mingle 272 220 -
Simple:simple 196 144 -
ments and 594Kb of memory. It is hard shed a light on the resource usage. Devices from different manufacturers cannot be compared easily with each other [83]. The numbers here are also not reflective of the eventual design size in silicon. However, it is good to take a look and see where some improvements can be made in the design, and to explore different parameters.
It becomes clear from Table 6.8 that the entities which store data require most logic cells to be emulated. This concerns the retargeting engine, registers, and the interrupt manager. This is also the reason that the Altera Memory IP is used as the ram memory. It is unclear why the b mux takes such an amount of resources: it is only a 32-bit asynchronous multiplexer. The interrupt manager also requires storage for the interrupt hierarchy array and interrupt vector table. The retargeting engine is the largest entity in the design. The memory bits it uses are because of the Memory IP that is used to store the H-Array, AR-Stack and read values. Without this the design would not fit the FPGA. A brief design exploration is held to deter- mine the factors that affect its resource usage. The retargeting engine is designed with 4 parameters that affect the design. They are shown in Table6.9 along with the resource usage measured. The default instantiation of the device is: 32 AR-stacks with 8 entries each, 256-bit shift buffer, and a H-Array with 64 entries. The shift buffer has the most influence on the design size. Shifting and extracting the values takes a large amount of resources. There are actually two buffers; one to create the access vector during traverse-and-generate, which is copied to the actual buffer for shifting. This was intended to parallelise generating and shifting the access vec- tor, which was never implemented unfortunately. Also, the shift buffer operates at a slower clock speed (TCK) than the rest of the system. Hypothetically, this allows the buffer to be stored in memory. The next value to be shifted could be loaded well
Table 6.9: FPGA resource usage of RE entity in Quartus.
LC DLR LC DLR LC DLR LC DLR
Shift Buffer Size: 128 256 512 1024
4.364 966 6.790 1.352 12.514 2.122 22.636 3.660 AR-Stacks: 8 16 32 64 6.445 1.248 6.605 1.284 6.790 1.352 7.212 1.484 AR-Stack Size: 8 12 16 24 6.790 1.352 6.873 1.391 6.865 1.385 6.967 1.424 H-Array Size: 32 64 128 256 6.672 1.283 6.790 1.352 7.027 1.485 7.438 1.746
before it is needed, but extracting read values would take more time. The amount of stacks is the next most influential factor. This is likely due to amount of stack pointers needed, which are integers bound by the stack size (-1 to stack size). Increasing the other parameters does not affect the design as much, mostly because the data is stored in the memory block. The size of this memory block is not altered for the tests. The FPGA resource statistics give some insight into the size and complexity of each component. The numbers are not reflective of the actual hardware size if the dependability manager is made into silicon. Unfortunately, the processor was not compiled to a silicon design. This was not possible due to the use of the Altera IP. Because of this, there is also no information available about the power usage or maximum clock speed. The design exploration shows that the retargeting engine could be optimised to allow larger shift buffers. The current design fits the relatively small FPGA and it can operate at the 50MHz clock speed. The usage of Memory IP allowed the large high-level programs to be stored on the FPGA.