Frame vs Task-Level Parallelism

Figure 4.4 illustrates the difference between Task- and Frame-level concurrency and introduces the manner in which the event queue enables frame-level concurrency. Both Figure 4.4(a) and (b) show how firmware processes the completion of DMA-read

P roc ess D M A R ea d T im e E v e n t R e g . DM A Read B it Recv. B D s Ready B it Fetch Fram e s B it ...O th er EventB its S e nd B D s S e nd F ra m e S e nd F ra m e S e nd B D s R e cv. B D s Descriptors D one? HW Sets B it B itS e t? R un Tas k P ro c e s s e s M ark Ready to Fetch M ark Re ad y Upda te "Do ne" M a rker w HW M ay C learB it R e cv . B D s D M A R e a d R ing S e nd B D s S e nd F ra m e S e nd F ra m e S e nd B D s Process D M A RD (Event1) Process D M A R D (E vent2) S e nd B D s R e cv . B D s P roce ss D M A R e a d (1) S e nd B D s S e nd F ra m e S e nd F ra m e P ro ces s D M A R e ad (2 ) E v e n t Q u e u e D e Q (1) Recv BDs R eady (Event3) Fetch Fram es (Event4) Fetch Fram es (E vent5) D e Q (2 ) E nQ (3 ) E nQ (4 ) E nQ (5 ) R ecv . B D s D M A R ea d R ing S e nd B D s S e nd F ra m e S e nd F ra m e S e nd B D s E nQ (1) E nQ (2 ) T im e P ro c e s s e s (a ) E v e n t R e g is te r (T a s k ºL e v e l P a ra lle lis m ) (b ) E v e n t Q u e u e (F ra m e ºL e v e l P a ra lle lism )

Figure 4.4 Contrasting Task- and Frame-Level Parallelism.

hardware events. In the event register case, Figure 4.4(a) shows that the hardware sets the DMA-read bit in the event register, which in turn causes the firmware to dispatch the process-DMA-read event handler. The process-DMA-read event handler inspects each completed DMA-read descriptor. Each descriptor may require further handling with future events. In Figure 4.4, the DMA-read descriptors are the boxes labeled “Recv. BDs,” “Send BDs,” and so forth. For instance, the process-DMA- read handler sets the Fetch Frames bit of the event register if it determines that send buffer descriptors have arrived on the DMA channel. Notice that the process- DMA-read handler must process the entire series of available DMA-read descriptors

and that while it is executing, no other instances of the process-DMA-read handler may execute. The key observation regarding frame-level parallelism, however, is that the individual pieces of such events (in this case the DMA-read descriptors that are pending processing) are independent of each other.

Figure 4.4(b) presents the same series of pending DMA-read events but shows how the event queue mechanism dispatches concurrent processing of process-DMA- read event handlers. The figure indicates event creation with filled, black double arrows and event dispatch with tailed arrows that have narrow heads. The figure associates actions with events by indicating the event number in parentheses. In this case, two processors inspect the DMA-read ring separately. The first inspection determines that two DMA-read transactions have completed, while the second finds the subsequent three transactions. Each processor immediately dispatches separate process-DMA-read handlers. Notice that unlike Figure 4.4(a), the process-DMA- read handlers may process the “Recv. BDs” transaction and the “Send Frame” transactions concurrently. Hence, the event queue enables a new form of parallelism that the previous event register construct did not allow.