6. SUMMARY AND FUTURE WORK
6.2 Future Work
Although KLPG significantly increase delay fault test quality, its test size is a concern of industrial designs. One of the reasons is that KLPG uses static compaction while the traditional transition fault test uses sophisticated dynamic compaction. Experiments have shown that the care bit density in KLPG test patterns is significantly lower than that in transition fault test patterns, and this indicates a potentially much higher compaction rate for KLPG tests.
Noise can have increasing impact on circuit delays as transistor dimensions shrink [102]. Noise can be induced by capacitive or inductive coupling [55][57], heat [103], or power supply noise [98][99]. Some algorithms have been developed to generate the worst-case noise [54][56]. In fact, the future test generation and compaction algorithms should keep noise at a reasonably high level rather than maximize it, which may result in yield loss.
REFERENCES
[1] G. Aldrich and B. Cory, “Improving Test Quality and Reducing Escapes,”
Proceedings of Fabless Forum, Fabless Semiconductor Association, vol. 10 no. 1,
2003, pp. 34-35.
[2] P. Nigh, D. Vallett, A. Patel, J. Wright, F. Motika, D. Forlenza, R. Kurtulik and W. Chong, “Failure Analysis of Timing and IDDQ-Only Failures from the
SEMATECH Test Methods Experiment,” in Proc. IEEE International Test
Conference, Washington, DC, Oct. 1998, pp. 43-52.
[3] C. F. Hawkins, A. Keshavarzi, and J. M. Soden, “Reliability, Test and IDDQ
Measurements,” in Proc. IEEE International Workshop on IDDQ Testing,
Washington, DC, Nov. 1997, pp. 96-102.
[4] X. Lin, R. Press, J. Rajski, P. Reuter, T. Rinderknecht, B. Swanson and N. Tamarapalli, “High-Frequency, At-Speed Scan Testing,” IEEE Design & Test of
Computers, vol. 20, no. 5, Sept.-Oct. 2003, pp. 17-25.
[5] A. Carbine and D. Feltham, “Pentium Pro Processor Design for Test and Debug,” in Proc. IEEE International Test Conference, Washington, DC, Nov. 1997, pp. 294-303.
[6] T. W. Williams, R. Kapur, M. R. Mercer, R. H. Dennard and W. Maly, “IDDQ
Test: Sensitivity Analysis of Scaling,” in Proc. IEEE International Test
[7] K. S. Kim, S. Mitra and P. G. Ryan, “Delay Defect Characteristics and Testing Strategies,” IEEE Design & Test of Computers, vol. 20, no. 5, Sept.-Oct. 2003, pp. 8-16.
[8] J. Gatej, L. Song, C. Pyron, R. Raina, T. Munns, “Evaluating ATE Features in Terms of Test Escape Rates and Other Cost of Test Culprits,” in Proc. IEEE
International Test Conference, Baltimore, MD, Oct. 2002, pp. 1040-1048.
[9] J. C. M. Li and E. J. McCluskey, “Diagnosis of Sequence Dependent Chips,” in
Proc. IEEE VLSI Test Symposium, Monterey, CA, Apr. 2002, pp. 187-192.
[10] International Technology Roadmap for Semiconductors (ITRS), San Jose, CA, Semiconductor Industries Association, 2003.
[11] S. R. Nassif, “Modeling and Analysis of Manufacturing Variations,” in Proc.
IEEE Custom Integrated Circuits Conference, San Diego, CA, May 2001, pp.
223-228.
[12] X. Lu, Z. Li, W. Qiu, D. M. H. Walker and W. Shi, “PARADE: PARAmetric Delay Evaluation Under Process Variation,” in Proc. International Symposium
on Quality Electronic Design, San Jose, CA, Mar. 2004, pp. 276-280.
[13] S. R. Nassif, “Design for Variability in DSM Technologies,” in Proc.
International Symposium on Quality Electronic Design, San Jose, CA, Mar. 2000,
[14] V. Mehrotra, S. L. Sam, D. Boning, A. Chandrakasan, R. Vallishayee and S. Nassif, “A Methodology for Modeling the Effects of Systematic Within-Die Interconnect and Device Variation on Circuit Performance,” in Proc. ACM/IEEE
Design Automation Conference, Los Angeles, CA, Jun. 2000, pp. 172-175.
[15] R. B. Brawhear, N. Menezes, C. Oh, L. T. Pillage and M. R. Mercer, “Predicting Circuit Performance Using Circuit-level Statistical Timing Analysis,” in Proc.
ACM/IEEE European Conference on Design Automation, Paris, France, Mar.
1994, pp. 332-337.
[16] E. Acar, S. N. Nassif, L. Ying and L. T. Pileggi, “Assessment of True Worst Case Circuit Performance Under Interconnect Parameter Variations,” in Proc.
International Symposium on Quality Electronic Design, San Jose, CA, Mar. 2001,
pp. 431-436.
[17] A. Gattiker, S. Nassif, R. Dinakar and C. Long, “Timing Yield Estimation from Static Timing Analysis,” in Proc. International Symposium on Quality Electronic
Design, San Jose, CA, Mar. 2001, pp. 437-442.
[18] Z. Barzilai and B. K. Rosen, “Comparison of AC Self-Testing Procedures,” in
Proc. IEEE International Test Conference, Philadelphia, PA, Oct. 1983, pp. 89-
94.
[19] J. L. Carter, V. S. Iyengar and B. K. Rosen, “Efficient Test Coverage Determination for Delay Faults,” in Proc. IEEE International Test Conference, Washington, DC, Sept. 1987, pp. 418-427.
[20] G. L. Smith, “Model for Delay Faults Based Upon Paths,” in Proc. IEEE
International Test Conference, Philadelphia, PA, Oct. 1985, pp. 342-349.
[21] K. Heragu, V. D. Agrawal and M. L. Bushnell, “Statistical Methods for Delay Fault Coverage Analysis,” in Proc. VLSI Design Conference, New Delhi, India, Jan. 1995, pp. 166-170.
[22] J. Waicukauski, E. Lindbloom, B. K. Rosen and V. S. Iyengar, “Transition Fault Simulation,” IEEE Design & Test of Computers, vol. 4, no. 5, Apr. 1987, pp. 32- 38.
[23] K. T. Cheng, S. Devadas and K. Keutzer, “Delay-Fault Test Generation and Synthesis for Testability Under a Standard Scan Design Methodology,” IEEE
Transactions on Computer-Aided Design of Integrated Circuits and Systems, vol.
12, no. 8, Aug. 1993, pp. 1217-1231.
[24] K. T. Cheng, “Transition Fault Testing for Sequential Circuits,” IEEE
Transactions on Computer-Aided Design of Integrated Circuits and Systems, vol.
12, no. 12, Dec. 1993, pp. 1971-1983.
[25] K. T. Cheng, “Test Generation for Delay Faults in Non-Scan and Partial Scan Sequential Circuits,” in Proc. IEEE/ACM International Conference on Computer
Aided Design, Santa Clara, CA, Nov. 1992, pp. 554-559.
[26] B. Koenemann, C. Barnhart, B. Keller, T. Snethen, O. Farnsworth and D. Wheater, “A SmartBIST Variant with Guaranteed Encoding,” in Proc. IEEE
[27] S. Mitra and K. S. Kim, “X-Compact: An Efficient Response Compaction Technique for Test Cost Reduction,” in Proc. IEEE International Test
Conference, Baltimore, MD, Oct. 2002, pp. 311-320.
[28] S. Mitra and K. S. Kim, “XPAND: Deterministic Test Generation with Very Few Scan Pins and Lots of Scan Chains,” Technical Report, Santa Clara, CA, Intel Corporation, 2003.
[29] J. Rajski, J. Tyszer, M. Kassab, N. Mukherjee, R. Thompson, K. H. Tsai, A. Hertwig, N. Tamarapalli, G. Mrugalski, G. Eide and J. Qian, “Embedded Deterministic Test for Low Cost Manufacturing Test,” in Proc. IEEE
International Test Conference, Baltimore, MD, Oct. 2002, pp. 301-310.
[30] B. R. Benware, R. Madge, C. Lu and R. Daasch, “Effectiveness Comparisons of Outlier Screening Methods for Frequency Dependent Defects on Complex ASICs,” in Proc. IEEE VLSI Test Symposium, Apr. 2003, pp. 39-46.
[31] R. R. Montanes and J. P. Gyvez, “Resistance Characterization for Weak Open Defects,” IEEE Design & Test of Computers, vol. 19, no. 5, Sept. 2002, pp. 18- 25.
[32] E. S. Park, M. R. Mercer and T. W. Williams, “Statistical Delay Fault Coverage and Defect Level for Delay Faults,” in Proc. IEEE International Test Conference, Washington, DC, Sept. 1988, pp. 492-499.
[33] C. W. Tseng and E. J. McCluskey, “Multiple-Output Propagation Transition Fault Test,” in Proc. in Proc. IEEE International Test Conference, Baltimore, MD, Oct. 2001, pp. 358-366.
[34] V. Iyengar, B. K. Rosen and I. Spillinger, “Delay Test Generation 1 – Concepts and Coverage Metrics,” in Proc. IEEE International Test Conference, Washington, DC, Sept. 1988, pp. 857-866.
[35] T. W. Williams, B. Underwood and M. R. Mercer, “The Interdependence Between Delay-Optimization of Synthesized Networks and Testing,” in Proc.
ACM/IEEE Design Automation Conference, San Francisco, CA, June 1991, pp.
87-92.
[36] G. M. Luong and D. M. H. Walker, “Test Generation for Global Delay Faults,” in Proc. IEEE International Test Conference, Washington, DC, Oct. 1996, pp. 433-442.
[37] W. Maly, “Computer-Aided Design for VLSI Circuit Manufacturability,”
Proceedings of the IEEE, vol. 78, no. 2, Feb. 1990, pp. 356-392.
[38] D. M. H. Walker, “Tolerance of Delay Faults,” in Proc. IEEE International
Workshop on Defect and Fault Tolerance in VLSI Systems, Dallas, TX, Nov.
1992, pp. 207-216.
[39] M. Sivaraman and A. J. Strojwas, “Delay Fault Coverage: A Realistic Metric and an Estimation Technique for Distributed Path Delay Faults,” in Proc. IEEE/ACM
International Conference on Computer Aided Design, San Jose, CA, Nov. 1996,
[40] J. J. Liou, L. C. Wang and K. T. Cheng, “On Theoretical and Practical Considerations of Path Selection for Delay Fault Testing,” in Proc. IEEE/ACM
International Conference on Computer Aided Design, San Jose, CA, Nov. 2002,
pp. 94-100.
[41] A. K. Majhi, V. D. Agrawal, J. Jacob and L. M. Patnaik, “Line Coverage of Path Delay Faults,” IEEE Transactions on Very Large Scale Integration (VLSI)
Systems, vol. 8, no. 5, Oct. 2000, pp. 610-613.
[42] A. Murakami, S. Kajihara, T. Sasao, I. Pomeranz and S. M. Reddy, “Selection of Potentially Testable Path Delay Faults for Test Generation,” in Proc. IEEE
International Test Conference, Atlantic City, NJ, Oct. 2000, pp. 376-384.
[43] M. Sharma and J. H. Patel, “Finding a Small Set of Longest Testable Paths that Cover Every Gate,” in Proc. IEEE International Test Conference, Baltimore, MD, Oct. 2002, pp. 974-982.
[44] C. J. Lin and S. M. Reddy, “On Delay Fault Testing in Logic Circuits,” IEEE
Transactions on Computer-Aided Design of Integrated Circuits and Systems, vol.
6, no. 9, Sept. 1987, pp. 694-701.
[45] J. Benkoski, E. V. Meersch, L. J. M. Claesen and H. D. Man, “Timing Verification Using Statically Sensitizable Paths,” IEEE Transactions on
Computer-Aided Design of Integrated Circuits and Systems, vol. 9, no. 10, Oct.
[46] P. McGeer and R. K. Brayton, “Efficient Algorithms for Computing the Longest Viable Path in a Combinational Network,” in Proc. ACM/IEEE Design
Automation Conference, Las Vegas, NV, Jun. 1989, pp. 561-567.
[47] H. Chang and J. A. Abraham, “VIPER: An Efficient Vigorously Sensitizable Path Extractor,” in Proc. ACM/IEEE Design Automation Conference, Dallas, TX, June 1993, pp. 112-117.
[48] K. Fuchs, M. Pabst and T. Rossel, “RESIST: A Recursive Test Pattern Generation Algorithm for Path Delay Faults Considering Various Test Classes,”
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, vol. 13, no. 12, Dec. 1994, pp. 1550-1562.
[49] M. P. Kusko, B. J. Robbins, T. J. Koprowski and W. V. Huott, “99% AC Test Coverage Using Only LBIST on the 1GHz IBM S/390 zSeries 900 Microprocessor,” in Proc. IEEE International Test Conference, Baltimore, MD, Oct. 2001, pp. 586-592.
[50] J. Saxena, K. M. Butler, J. Gatt, R. Raghuraman, S. P. Kumar, S. Basu, D. J. Campbell and J. Berech, “Scan-Based Transition Testing – Implementation and Low Cost Test Challenges,” in Proc. IEEE International Test Conference, Baltimore, MD, Oct. 2002, pp. 1120-1129.
[51] J. Savir, “Skewed-Load Transition Test: Part I, Calculus,” in Proc. IEEE
International Test Conference, Baltimore, MD, Sept. 1992, pp. 705-713.
[52] S. Patel and J. Savir, “Skewed-Load Transition Test: Part II, Coverage,” in Proc.
[53] J. Savir and S. Patel, “Broad-Side Delay Test,” IEEE Transactions on Computer-
Aided Design of Integrated Circuits and Systems, vol. 13, no. 8, Aug. 1994, pp.
1057-1064.
[54] W. Y. Chen, S. K. Gupta and M. A. Breuer, “Test Generation for Crosstalk- Induced Delay in Integrated Circuits,” in Proc. International Test Conference, Atlantic City, NJ, Sept. 1999, pp. 191-200.
[55] B. Choi and D. M. H. Walker, “Timing Analysis of Combinational Circuits Including Capacitive Coupling and Statistical Process Variation,” in Proc. VLSI
Test Symposium, Montreal, Canada, Apr. 2000, pp. 49-54.
[56] A. Krstic, J. J. Liou, Y. M. Jiang and K. T. Cheng, “Delay Testing Considering Crosstalk-Induced Effects,” in Proc. International Test Conference, Baltimore, MD, Oct. 2001, pp. 558-567.
[57] W. Moore, G. Gronthoud, K. Baker and M. Lousberg, “Delay-Fault Testing and Defects in Sub-Micron ICs – Does Critical Resistance Really Mean Anything?” in Proc. International Test Conference, Atlantic City, NJ, Oct. 2000, pp. 95-104. [58] K. T. Cheng and H. C. Chen, “Classification and Identification of Non-Robust
Untestable Path Delay Faults,” IEEE Transactions on Computer-Aided Design of
Integrated Circuits and Systems, vol. 15, no. 8, Aug. 1996, pp. 845-853.
[59] K. T. Cheng and H. C. Chen, “Delay Testing for Non-Robust Untestable Circuits,” in Proc. IEEE International Test Conference, Baltimore, MD, Oct. 1993, pp. 954-961.
[60] W. K. C. Lam, A. Saldanha, R. K. Brayton and A. L. Sangiovanni-Vincentelli, “Delay Fault Coverage and Performance Trade-Offs,” in Proc. ACM/IEEE
Design Automation Conference, Dallas, TX, Jun. 1993, pp. 446-452.
[61] J. B. Brockman and S. W. Director, “Predictive Subset Testing: Optimizing IC Parametric Performance Testing for Quality, Cost, and Yield,” IEEE
Transactions on Semiconductor Manufacturing, vol. 2, no.3, Aug. 1989, pp. 104-
113.
[62] X. Lu, Z. Li, W. Qiu, W. Shi and D. M. H. Walker, “Longest Path Selection for Delay Test Under Process Variation,” in Proc. Asian and South Pacific Design
Automation Conference, Yokohama, Japan, Jan. 2004, pp. 98-103.
[63] W. Qiu, X. Lu, J. Wang, Z. Li, D. M. H. Walker and W. Shi, “A Statistical Fault Coverage Metric for Realistic Path Delay Faults,” in Proc. IEEE VLSI Test
Symposium, Napa Valley, CA, Apr. 2004, pp. 37-42.
[64] V. R. Sar-Dessai and D. M. H. Walker, “Resistive Bridge Fault Modeling, Simulation and Test Generation,” in Proc. IEEE International Test Conference, Atlantic City, NJ, Sept. 1999, pp. 596-605.
[65] Z. Li, X. Lu, W. Qiu, W. Shi and D. M. H. Walker, “A Circuit Level Fault Model for Resistive Opens and Bridges,” in Proc. IEEE VLSI Test Symposium, Napa Valley, CA, Apr. 2003, pp. 379-384.
[66] Z. Li, X. Lu, W. Qiu, W. Shi and D. M. H. Walker, “A Circuit Level Fault Model for Resistive Bridges,” ACM Transactions on Design Automation of Electronic
[67] X. Lu, Z. Li, W. Qiu, D. M. H. Walker and W. Shi, “A Circuit Level Fault Model for Resistive Shorts of MOS Gate Oxide,” in Proc. IEEE International Workshop
on Microprocessor Test and Verification, Austin, TX, Sept. 2004, pp. 97-102.
[68] W. Qiu, X. Lu, Z. Li, D. M. H. Walker and W. Shi, “CodSim – A Combined Delay Fault Simulator,” in Proc. IEEE International Symposium on Defect and
Fault Tolerance in VLSI Systems, Boston, MA, Nov. 2003, pp. 79-86.
[69] W. Qiu, Z. Li, X. Lu, W. Shi and D. M. H. Walker, “Combined Delay Fault Modeling and Simulation,” in Proc. Semiconductor Research Corporation
Technical Conference, Dallas, TX, Aug. 2003, No. 1.7.
[70] W. Qiu and D. M. H. Walker, “An Efficient Algorithm for Finding the K Longest Testable Paths Through Each Gate in a Combinational Circuit,” in Proc. IEEE
International Test Conference, Charlotte, NC, Sept. 2003, pp. 592-601.
[71] D. Belete, A. Razdan, W. Schwarz, R. Raina, C. Hawkins and J. Morehead, “Use of DFT Techniques in Speed Grading a 1GHz+ Microprocessor,” in Proc. IEEE
International Test Conference, Baltimore, MD, Oct. 2002, pp. 1111-1119.
[72] S. D. Millman and E. J. McCluskey, “Detecting Bridging Faults with Stuck-At Test Sets,” in Proc. IEEE International Test Conference, Washington, DC, Sept. 1988, pp. 773-783.
[73] N. A. Touba and E. J. McCluskey, “Pseudo-Random Pattern Testing of Bridging Faults,” in Proc. IEEE International Conference on Computer Design, Austin, TX, Oct. 1997, pp. 54-60.
[74] B. Chess and T. Larrabee, “Logic Testing of Bridging Faults in CMOS Integrated Circuits,” IEEE Transactions on Computers, vol. 47, no. 3, Mar. 1998, pp. 338- 345.
[75] J. P. Cusey and J. H. Patel, “BART: A Bridging Fault Test Generator for Sequential Circuits,” in Proc. IEEE International Test Conference, Washington, DC, Nov. 1997, pp. 838-847.
[76] M. Spica, M. Tripp and R. Roeder, “A New Understanding of Bridge Defect Resistances and Process Interactions from Correlating Inductive Fault Analysis Predictions to Empirical Test Results,” in Proc. IEEE Defect Based Testing, Marina Del Rey, CA, Apr. 2001, pp. 11-16.
[77] W. N. Li, S. M. Reddy and S. K. Sahni, “On Path Selection in Combinational Logic Circuits,” IEEE Transactions on Computer-Aided Design of Integrated
Circuits and Systems, vol. 8, no. 1, Jan. 1989, pp. 56-63.
[78] Y. Shao, S. M. Reddy, I. Pomeranz and S. Kajihara, “On Selecting Testable Paths in Scan Designs,” in Proc. IEEE European Test Workshop, Corfu, Greece, May 2002, pp. 53-58.
[79] I. Pomeranz, S. M. Reddy and P. Uppaluri, “NEST: A Nonenumerative Test Generation Method for Path Delay Faults in Combinational Circuits,” IEEE
Transactions on Computer-Aided Design of Integrated Circuits and Systems, vol.
[80] K. Fuchs, F. Fink and M. H. Schulz, “DYNAMITE: An Efficient Automatic Test Pattern Generation System for Path Delay Faults,” IEEE Transactions on
Computer-Aided Design of Integrated Circuits and Systems, vol. 10, no. 10, Oct.
1991, pp. 1323-1355.
[81] J. A. Bell, “Timing Analysis of Logic-Level Digital Circuits Using Uncertainty Intervals,” M. S. Thesis, Department of Computer Science, Texas A&M University, 1996.
[82] R. Stewart and J. Benkoski, “Static Timing Analysis Using Interval Constraints,” in Proc. IEEE International Conference on Computer-Aided Design, Santa Clara, CA, June 1991, pp. 308-311.
[83] P. Goel, “An Implicit Enumeration Algorithm to Generate Tests for Combinational Logic Circuits,” IEEE Transactions on Computers, vol. C-30, no. 3, Mar. 1981, pp.215-222.
[84] W. Qiu and D. M. H. Walker, “Testing the Path Delay Faults of ISCAS85 Circuit c6288,” in Proc. IEEE International Workshop on Microprocessor Test and
Verification, Austin, TX, May 2003, pp. 19-24.
[85] M. Hansen, H. Yalcin and J. P. Hayes, “Unveiling the ISCAS-85 Benchmarks: A Case Study in Reverse Engineering,” IEEE Design & Test of Computers, vol. 16, no. 3, July-Sept. 1999, pp. 72-80.
[86] T. Kirkland and M. R. Mercer, “A Topological Search Algorithm for ATPG,” in
Proc. ACM/IEEE Design Automation Conference, Jun. 1987, Miami, FL, pp.
[87] W. T. Cheng and T. J. Chakraborty, “Gentest: An Automatic Test Generation System for Sequential Circuits,” IEEE Computer, vol. 22, no.4, Apr. 1989, pp. 43-49.
[88] T. M. Niermann and J. H. Patel, “HITEC: A Test Generation Package for Sequential Circuits,” in Proc. ACM/IEEE European Design Automation
Conference, Amsterdam, Netherlands, Feb. 1991, pp. 214-218.
[89] A. A. Thadhlani, “Realistic Fault Modeling and Quality Test Generation of Combined Delay Faults,” M. S. Thesis, Department of Computer Science, Texas A&M University, 2001.
[90] W. Qiu, J. Wang, D. M. H. Walker, D. Reddy, X. Lu, Z. Li, W. Shi and H. Balachandran, “K Longest Paths Per Gate (KLPG) Test Generation for Scan- Based Sequential Circuits,” in Proc. IEEE International Test Conference, Charlotte, NC, Oct. 2004, pp. 223-231.
[91] W. Qiu, J. Wang, X. Lu, Z. Li, D. M. H. Walker and W. Shi, “At-Speed Test for Path Delay Faults Using Practical Techniques,” in Proc. IEEE International
Workshop on Current and Defect Based Testing, Napa Valley, CA, Apr. 2004, pp.
61-66.
[92] J. Wang, Z. Yue, X. Lu, W. Qiu, W. Shi and D. M. H. Walker, “A Vector-Based Approach for Power Supply Noise Analysis in Test Compaction,” in Proc. IEEE
[93] J. Wang, X. Lu, W. Qiu, Z. Yue, S. Fancler, W. Shi and D. M. H. Walker, “Static Compaction of Delay Tests Considering Power Supply Noise,” in Proc. IEEE
VLSI Test Symposium, Palm Springs, CA, May 2005, pp. 235-240.
[94] E. M. Rudnick and J. H. Patel, “Efficient Techniques for Dynamic Test Sequence Compaction,” IEEE Transactions on Computers, vol. 48, no. 3, Mar. 1999, pp. 323-330.
[95] I. Pomeranz and S. M. Reddy, “COREL: A Dynamic Compaction Procedure for Synchronous Sequential Circuits with Repetition and Local Static Compaction,” in Proc. IEEE International Conference on Computer Design, Austin, TX, Sept. 2001, pp. 142-147.
[96] S. Y. Lee, B. Cobb, J. Dworak, M. R. Grimaila and M. R. Mercer, “A New ATPG Algorithm to Limit Test Set Size and Achieve Multiple Detections of All Faults,” in Proc. Design Automation and Test in Europe Conference and
Exhibition, Paris, France, Mar. 2002, pp. 94-99.
[97] J. Wingfield, J. Dworak and M. R. Mercer, “Function-Based Dynamic Compaction and Its Impact on Test Set Sizes,” in Proc. IEEE International
Symposium on Defect and Fault Tolerance in VLSI Systems, Boston, MA, Nov.
2003, pp. 167-174.
[98] K. L. Shepard and V. Narayanan, “Noise in Deep Submicron Digital Design,” in
Proc. IEEE/ACM International Conference on Computer Aided Design, San Jose,
[99] Y. M. Jiang and K. T. Cheng, “Analysis of Performance Impact Caused by Power Supply Noise in Deep Submicron Devices,” in Proc. ACM/IEEE Design
Automation Conference, New Orleans, LA, Jun. 1999, pp. 760-765.
[100] R. Ahmadi and F. N. Najm, “Timing Analysis in Presence of Power Supply and Ground Voltage Variations,” in Proc. IEEE/ACM International Conference on
Computer Aided Design, San Jose, CA, Nov. 2003, pp. 176-183.
[101] C. Tirumurti, S. Kundu, S. Sur-Kolay and Y. S. Chang, “A Modeling Approach for Addressing Power Supply Switching Noise Related Failures of Integrated Circuits,” in Proc. Design Automation and Test in Europe Conference and
Exhibition, Paris, France, Feb. 2004, pp. 1078-1083.
[102] T. M. Mak, A. Krstic, K. T. Cheng and L. C. Wang, “New Challenges in Delay Testing of Nanometer, Multigigahertz Designs,” IEEE Design & Test of
Computers, vol. 21, no. 3, May-Jun. 2004, pp. 241-248.
[103] S. Rusu, S. Seidel, G. Woods, D. Grannes, H. Muljono, J. Rowlette and K. Petrosky, “Backside Infrared Probing for Static Voltage Drop and Dynamic Timing Measurements,” in Proc. IEEE International Solid-State Circuits
VITA
Wangqi Qiu
1269-1-501 N. Zhongshan Rd. Shanghai 200065 People’s Republic of China E-mail: [email protected]
Wangqi Qiu was born in Shanghai, China on February 12, 1978. He obtained his B.S. in Computer Science from Fudan University, Shanghai, China in July 2000, and Ph.D. in Computer Science from Texas A&M University, College Station, TX in December 2006. His research interests are delay fault testing, automatic test pattern generation, timing analysis and optimization.