Texas Instruments Experiments

The design selected for the experiments is a controller with 5 clock domains. The fastest clock domain is 250 MHz. Delay tests are applied to the 250 MHz domain only. The controller is a 130 nm technology ASIC design and contains 738 K gates. The logic within the 250 MHz domain contains 597 K gates, not including embedded memories. According to the test configuration, the controller is a partial scan design and contains 8 scan chains for the 250 MHz domain, with 14 963 muxed scanned flip-flops in total, and these flip-flops are clocked with the system clock under both shift and functional mode. At-speed test can only be performed using launch-on-capture.

There are 24 devices included in the experiments. These devices marginally pass the transition fault test of the 250 MHz domain in production. Four delay test sets are used in the experiments:

1. (Critical) path delay test (generated by the KLPG tool, by removing the constraints that every gate/line must be covered), which tests 2 137 critical paths (longest non-robustly sensitizable paths) in the 250 MHz domain;

2. Regular transition fault test (generated by a commercial tool), which is the delay test in production;

makes random decisions and does not necessarily propagate transition faults through the easiest paths;

4. KLPG-1 test (generated by the KLPG tool).

Table 14 shows the test volume of each test. The volume of the randomized transition fault test is slightly higher than that of the regular one. Again, KLPG-1 has a significantly larger test volume.

Table 14. Test volume comparison in Texas Instruments experiments.

Test # of patterns

Path delay test 774

Regular TF 1 445

Randomized TF 1 471

KLPG-1 12 579

Figure 49 shows the speed binning results of the four delay test methodologies. It can be seen that for most devices, KLPG has the lowest Fmax, which means testing longer paths does result in slower speed. KLPG has two unique detects: devices 6 and 14. They pass the other tests but fail the KLPG test, given the 250 MHz specification. Devices 3, 4 and 24 do not fail any test, but KLPG is significantly slower. For these devices, the path delay test does not result in low Fmax, which indicates that these devices are likely to contain small defects that have no critical paths going through and KLPG detects them through longer paths than the transition fault tests do. These paths may still be much shorter than any critical paths. The results prove the benefit of testing the longest paths through each gate/line.

240.0 245.0 250.0 255.0 260.0 265.0 270.0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 Device ID Fmax ( M H z) Path Delay Regular TF Random TF KLPG-1

Figure 49. Fmax comparison using four delay test methodologies.

Randomized transition fault test does not seem to have significant benefits. Compared to the regular transition fault test, it results in slightly lower Fmax for five devices but slightly higher Fmax for 10 devices. Interestingly, it gets a unique detect (device 21) though the difference from KLPG or path delay test is very small. The test may sensitize a path or a set of paths that is longer than the paths generated by KLPG, and it can be more likely if a delay fault can only be detected through a set of paths, because KLPG deterministically propagates transitions through single long paths. Alternatively, it can be a fault that is not modeled in KLPG, such as a resistive bridging fault, which is fortuitously detected by the randomized transition fault test. It can also be a power supply noise issue, because transition fault tests are highly compacted so that more

switches are activated by a single test pattern, which may result in higher power supply noise and slower paths.

It is interesting to look at the path delay test results. For ~1/3 of the devices, the path delay test results in the lowest Fmax. This is straightforward because if a device is defect-free, or the device contains only undetectable faults, e.g. all paths through a small defect are very short so that no path is slow (this fault can be detected using higher-than- functional-speed test), the actual longest path is the one that determine the speed of the circuit. Because of process variation, many critical paths can be the actual longest path. KLPG-1 tests the longest path (one that has the highest probability to be the actual longest path) through each potential fault site, but the number of globally longest paths may not be enough. The path delay patterns test 2 137 critical paths so that it is much more likely to hit the actual longest one. Devices 5, 7, 8, 10, 11, 17, 18 and 20 are likely to be in this category. Theoretically, if more critical paths are tested, almost all defect free devices should drop into this category.

However, Fmax of the path delay test for devices 15, 19, 22 and 24 is significantly higher than that of the other tests. Possible reasons can be:

1. Huge process variation;

2. Small defects that the path delay test misses; 3. Fortuitous detects by other tests;

4. Lower power supply noise than other tests.

Huge process variation can cause the path delay test to miss the actual longest path, which may be sensitized by other tests by luck simply because they have more test

patterns. However, this is not very likely by looking at the behavior of other devices in our experiments.

Small defects are the most likely reason because both transition and KLPG tests cover the whole circuit while the path delay test does not. All the critical paths that are sensitized by the path delay patterns can be within a small area of the circuit. If a small defect exists out of this area, the path delay test may miss it while it can be easily detected by KLPG, and sometimes by the transition fault test either.

If the small defect behave as a bridging fault that only causes extra delay, it is also a fortuitous detect by the other three tests as none of them targets bridging faults explicitly. In fact, KLPG is good at catching resistive bridging faults fortuitously, as the simulation results show. 178 180 182 184 186 188 190 1 2 3 4 5 6 7 8 9 10 TF Test Group Fma x ( M H z) Device 8 Device 22 Device 24 Most devices behave like Device 8

Figure 50. “Signatures” of devices 22 and 24.

transition test patterns are divided evenly into 10 groups by their original order, and speed binning is run for each group, at a lower VDD (1.2V, compared to the nominal 1.5V) to exaggerate the difference. Figure 50 shows Fmax curves for devices 22 and 24, and the curves can be considered “signatures”. More than 50% of the devices behave like device 8, with an “M-V” shaped signature. However, devices 22 and 24 behave differently. Device 22 is slower than expected for pattern groups 2 and 9. It is likely to contain a small defect that is only sensitized by some patterns in these two groups, but not by the path delay test. Similarly, device 24 seems to have a small defect too because it is slow for groups 3, 8 and 9.

180 182 184 186 188 190 192 194 1 2 3 4 5 6 7 8 9 10 TF Test Group Fma x ( M H z) Device 8Device 15 Device 19 Device 5 Most devices behave like Device 8

Figure 51. “Signatures” of devices 15 and 19.

However, devices 15 and 19 do not have obviously abnormal signatures, as shown in Figure 51. They behave slightly differently from device 8, which represents more than 50% of the devices but similarly to device 5, which seems to be a good device according

to the results shown in Figure 49. The signatures of devices 15 and 19 are completely bounded by the signatures of devices 5 and 8. It is hard to say whether they contain small defects or not from their signatures.

Power supply noise may be another reason [98][99]. Due to this reason, paths under the transition fault tests may be slower than paths under the path delay test. This is because: care bit density of the transition fault test patterns is significantly higher than that of the path delay test patterns Î a transition fault test pattern may cause more switching activities in the circuit Î it is likely to have higher power supply noise Î paths sensitized by a transition fault test pattern become significantly slower than their nominal delays due to the power supply noise [100]. This can be more sensitive as power supply voltage decreases in deep sub-micron (DSM) designs [101].

Figure 52 is the care bit density comparison of the path delay test and transition fault test without random fill. Every point represents the average number for 50 patterns. Because the care bit density is unknown with regular setting (with random fill) in the commercial tool, the random fill switch is turned off in this experiment. However, this introduces a 1.6x test volume increase (1 445 patterns with random fill turned on vs. 2 331 patterns with random fill turned off). Average care bit density of the transition fault test without random fill is 4.59%, and it can be 1.6x higher, which is ~7.4%, for the transition fault test with random fill. In reality, this number can be slightly lower than 7.4% because some care bits overlap during compaction (it is not always a 1 or 0 compacted with an X). However, this number is close to the production transition fault test value, which really matters.

0 2 4 6 8 10 12 14 16 18 20 0 5 10 15 20 25 30 35 40 45 Pattern group (every point represents 50 patterns)

A v er ag e ca re b it d e n s it y ( % )

Transition w/o random fill Path Delay

Care bit density of transition fault test with random fill (which is in production) may be ~1.6x higher

Figure 52. Comparison of care bit density (TF vs. path delay).

Compared to the high care bit density of the transition fault test, it is significantly lower for the path delay test (2.23%). Furthermore, the maximum care bit density of the transition fault test pattern (without random fill) is 38.66% (pattern #3), which is much higher than that of the path delay test patterns (3.91%). On average, each path delay test pattern tests only 2.74 paths. It is reasonable to expect a higher level of power supply noise introduced by a transition fault test pattern.

Figure 53 shows the comparison between the transition fault test (without random fill) and the KLPG-1 test. The average care bit density of the KLPG-1 test is 2.60% and the maximum is 12.09% (pattern #1). Like the path delay test, the care bit density of the KLPG-1 test does not drop significantly from the first pattern to the last, which happens to most structural tests like stuck-at and transition fault tests. From this data, it seems that the KLPG-1 test does not have high power supply noise either, if all of our

assumptions are valid. However, the KLPG-1 test does well in the Fmax comparison. Therefore, power supply noise may not be the main reason that Fmax of the path delay test is significantly higher for four devices, or our assumptions that the transition fault test cause much more transition activities are invalid for this device.

0 2 4 6 8 10 12 14 16 18 20 0 50 100 150 200 250 Pattern group (every point represents 50 patterns)

A ver ag e car e b it d e n s it y ( % )

Transition w/o random fill KLPG-1

Figure 53. Comparison of care bit density (TF vs. KLPG-1).

To get additional data, the following experiment was performed. The first 200 transition fault test patterns in production are selected as “noise” source, because these patterns are assumed to have the highest care bit density so that they are likely to be the “noisiest”. The original path delay test patterns are considered “quiet” due to the large amount of don’t care bits (min: 96.08% max 98.90%). For each “quiet” path delay test pattern, one of the “noisy” transition fault test patterns that has fewest conflicting bits is selected as the noise source for that “quiet” path delay test pattern. The two patterns are then “compacted” together. Figure 54 shows an example. If two patterns contain

conflicting bits, such as input bit #4 in this example, the path delay test pattern bit is kept, so that the target paths of the path delay test pattern are still sensitized. In this way, “noise” is introduced into the “quiet” pattern because more switching activities may happen in the circuit. The expected output of the “noisy” path delay test pattern keeps the same as that of the “quiet” pattern. Bits that are not the destinations of the target paths are all masked. This is because if other paths are fortuitously sensitized, it may result in an unfair comparison between “noisy” and “quiet” path delay test patterns.

1 0 1 1 1 1 0 1 1 X X 1 0 X X X 1 X 1 0 1 0 1 X X 1 X “Noisy” TF test pattern

“Quiet” path delay test pattern

“Noisy” path delay test pattern

Figure 54. Making path delay tests more “noisy”.

Figure 55 shows the Fmax comparison of the “noisy” path delay test and variety of tests that have different noise level: tests that fill the don’t care bits with random values, all 1’s-fill and all 0’s. The shift frequency is 25 MHz so that the voltage drop during launch and capture caused by shift can be neglected. The first four devices (devices 15,

19, 22, 24) are the ones that have significantly higher Fmax using randomly filled path delay test. This experiment uses a low VDD (1.2V, compared to the nominal 1.5V) to exaggerate the difference. The other devices (devices 101-107) are slow devices only under low VDD (these devices are separate from the 24 devices that are used in previous experiments). 170.0 180.0 190.0 200.0 210.0 220.0 1 2 3 4 5 6 7 8 9 10 11 Device ID Fmax ( M H z) TF Noise Random Fill 1-Fill 0-Fill 15 19 22 24 101 102 103 104 105 106 107 Low VDD (1.2V)

Figure 55. Fmax comparison of “noisy” and “quiet” path delay tests.

It can be seen that for most devices “noisy” pattern do result in lower Fmax, but the difference is small. The most possible reason is that our assumption that the transition fault patterns with high care bit density make more switching activities may be wrong. For 7 out of 11 devices, Fmax with 0-fill is equal or lower than Fmax with random fill. This breaks our assumption that 1-fill or 0-fill makes fewer switches in the circuit than

random fill. The number of switching activities in these devices may not vary significantly with different fill methods. As a result, the path delay test compared in Figure 49 may not be as “quiet” as assumed. From the data, the conclusion is that these four devices are more likely to contain small delay defects that the path delay test misses.

In summary, Figure 49 shows that Fmax of applying KLPG-1 alone is close to the lower bound. It can be even closer if KLPG-1 is combined with the path delay test. However, test volume is a concern at this moment. Before powerful compaction methodologies are developed for KLPG, combining the transition fault and path delay tests may be a good choice. It does better than applying the transition fault test alone and the test volume is still kept at a low level. Alternatively, the transition fault test can be the top-off test for the path delay test; to get a lower combined test volume.