Hardware-based evo-devo NNs

Researchers have sought to create hardware-based evo-devo neural network systems capable of evolving, developing and learning in situ, adapting to the given problems and environments. These are called POE systems as they are aimed to show these capabilities in all three aspects of Phylogeny, Ontogeny and,

Epigenesis of an organism [342]. POE systems can use online development that brings fault-tolerance and self-repair features to the neural networks [370] and similar systems. Online development in these systems allows developmental process to use neural activity and other environmental factors as useful information for adaptivity. It can also provide evolutionary process with useful fitness information during development and learning. Evo-devo spiking neural networks that could be implemented on the POEtic chip [94, 366, 270, 271] would be good examples of such systems. PEOtic Chip is a custom-designed reconfigurable integrated circuit as a hardware platform for POE systems. It is based on a layered architecture known as POEtic tissue [370] that dedicates three separate layers to Phylogenic, Ontogenic and, Epigenesis processes.

One of the challenges in the field of hardware-based evo-devo systems is the difficulties of imple- menting cell devision in silicon [361]. Although reconfigurable chips and FPGAs provide some flexi- bility to achieve similar processes, cell devision remained a challenge. Most of the solutions implicitly allow new cells to take over hardware resources without explicitly dividing anything as such alteration of hardware substrate is physically not possible [361]. Many approaches abstract out the cell division process into the cell differentiation process or reduce it to the simpler process of self-replication [361]. Tempesti et. al. reviewed a number of usual approaches to hardware-based cell division and differentia- tion in [361].

Routing of the signals is another challenge in hardware-base evo-devo NNs. POEtic tissue address this by dedicating two set of routing resources on separate layers for local and global circuit switching and communication between cells [94, 366, 270, 271]. Thoma and Sanchez reviewed a number of hardware-based routing algorithms for circuit-switched communication between cells in [362]. Other systems tend to use packet-switched NOCs (Network-on-Chips) as they allow much higher connectivity density but may suffer from packet delays and jitter noise depending on the network activity [147, 272, 58, 62, 60, 59].

Evolvable hardware has been previously used for evolving spiking neural microcircuits in FPGAs. For example, Upegui et al. evolved a fully connected recurrent spiking neural network of 30 simplified LIF neurons with 30 synapses each on a Xilinx Spartan FPGA [374]. However, the number of neurons and synapses, general architecture of the network, and the neuron parameters were fixed during the evolution and no developmental process was used. There are also other hardware-based adaptive neural systems that may be modified for evo-devo neural networks [60, 62]. However these are not specifically designed or suited for intrinsic developmental processes.

Inspired by the seminal work of Thomson [364] with a cellular structure on Xilinx XC6264, several multi-cellular developmental systems for FPGAs have been designed by Haddow and Tufte, Liu, Miller and Tyrrell, Gordon, and many others, cited above and in [311]. One of the first reported works on hardware-based evo-devo neural networks is CAM-Brain project by DeGaris et.al. [120, 74], based on Cellular Automata and implemented in Xilinx XC6264 FPGAs. They report experiments on a system of about 1000 neurons.

consisting of a 4x4 array of POEtic chips [370]. Their model is based on an optimised serial implemen- tation of LIF neuron model with bio-plausible synapse and STDP (Spike-Time-Dependent-Plasticity) learning [366] on the reconfigurable substrate of POEtic tissue that allows neighbouring cells to recon- figure each other for fault-tolerance and self-repair. Unfortunately, only one such neuron can be fit in a single POEtic chip due to size limitations of the actual POEtic chips. Therefore, time-multiplexing was used to simulate a network of 10,000 neurons. This, however requires loading the parameters and neuron variables into the chips every 150 cycles for 625 times for one network update. This was still fast enough for realtime processing of a 384x288 pixel video stream at 50 frames/sec. However, at this stage, the developmental and evolutionary potentials of the POEtic tissue was not exploited fully. Their implementation uses a parallel hardware implementation of breath-first search algorithm for dynamic routing of axons and dendrites that is initiated by the unconnected neuron input and outputs. Allen et. al. [6] also report implementing a very small network consisting of 3 spiking neurons capable of STDP learning and evolution on an FPGA and a POEtic chip.

Later, Roggen et. al. worked on the evo-devo features of the PEOtic tissue and presented a com- prehensive review of the hardware-based evo-devo systems including neural networks in [311]. They introduced a new classification of developmental systems, and stressed the importance of hardware- based (intrinsic), online, cellular and distributed developmental systems arguing that a lot of desired features of developmental systems such as adaptivity, fault-tolerance, scalability, speed, and robustness are achievable with such evo-devo systems. They also proposed a hardware based evo-devo spiking neu- ral network system, based on diffusion of morphogens with very simplistic cell chemistry and neuron model, and applied it to character recognition and robot navigation tasks successfully. The largest net- work they implemented comprises a 8x8 grid of 64 neurons and a maximum of 12 synapses (inputs) per neurons. They demonstrated improvements in fault-tolerance, and scalability of the system compared to using a directly encoded genome. Although their design was generic and could be implemented in any reconfigurable platform, their system was initially designed for POEtic chip [370], and prototyped on a FPGA for experiments [310, 311]. However, the range and pattern of neurons connectivity were limited to six fixed local connectivity patterns and a simplistic leaky integrate and fire soma model was used in their implementation [311].

Recently, Upegui et al. introduced a dynamic routing algorithm to produce nature inspired activity dependent synaptogenesis in the cellular bespoke reconfigurable chip, Ubichip [375, 380]. Ubichip is a reconfigurable platform, as part of a greater project call Perplexus, aiming at ubiquitous and embedded computing for complex systems [324, 379, 375, 378, 380]. They showed that the network activity infor- mation can be used effectively for neurogenesis and the resulting network architectures resembled those of biological neural networks. Although their hardware-based routing algorithm is a very fast implemen- tation of its kind, their current design may face some scaling limitations (due to using long combinatorial signals sensitive to delays) [375, 380]. Moreover the number of possible input synapses for each neuron is fixed and defined a priori [375, 380].

BRACE mixed-signal reconfigurable custom SNN chip. The FPGA prototype of the EMBRACE chip is able to evolve synaptic weights and neuron thresholds of a pre-specified network architecture. The analog LIF neurons are modelled by soft core processors on the FPGA and a NOC (Network-on-Chip) is responsible for interneuron spike communications. The EMBRACE system successfully evolved spiking XOR, an inverted pendulum controller, and a classifier for Wisconsin breast cancer dataset. Although many feasibility measures such as scalability, fault-tolerance, robustness, performance and hardware cost are considered, bio-plausibility is not a priority in EMBRACE-FPGA project and the system does not use a developmental process or any bio-plausible features other than spiking neurons and a genetic algorithm for achieving scalability and fault-tolerance.

Yet none of these models are quite suitable for a developmental neural microcircuit capable of regeneration and growth on FPGA. Evidence suggests that structural plasticity [65] and wiring delays [66] play major roles in the brain. The placement and wiring of the neurons are also optimised for the high interconnectivity in the brain [64]. In contrast, most of the existing evolvable hardware neural network models (e.g. [311, 374, 380, 271]) are not capable of flexible neurite growth in silicon. They either are typically restricted in terms of number of inputs per neuron or impose constraints on the patterns of connectivity and/or placement on the actual chip mostly due to implementation issues. Some of them do not allow heterogeneous networks with flexible parametric neurons and learning rules as important bio-plausible features or use very simplified developmental processes. They either keep the silicon area low and gain a high speed by using excessively simplified neuron models or use bio-plausible models and quickly run out of silicon area forcing them to use time-multiplexing. Although most of them are originally designed for custom chips (Ubichip [375, 380], and POEtic chip [370] for example) they ended up being prototyped on FPGAs due to availability issues such as high NRE costs of ASICs and even after fabrication of the actual chips they are limited to small-scale chips mainly due to financial reasons.