HDL based specification methods use a standard HDL such as Verilog as an input to the tool.
5.4.1
Chainworks
Chainworks was developed by Silistix Ltd, UK. It is a tool suite comprising of various software tools that help to design and synthesize a customized on-chip interconnect fabric between various IP blocks using self-timed (clockless) circuits. [66]
5.4.1.1 Overview
"The CHAINworks tool suite takes a description of the initiator and target ports of an System on Chip (SoC) design and synthesizes a structural netlist for a CHAIN interconnect. The suite comprises three tools: CHAINdesigner™ for design explo- ration, CHAINcompiler™ for CHAIN fabric synthesis, and CHAINlibrary™, which is an interconnect component library." [67] CHAINdesigner uses a description of the
initiator and the target ports of the design as an input to perform synthesis and generate a structural netlist for the interconnect fabric. It is CHAINcompiler which then uses this structured netlist and components from the CHAINlibrary to perform logic synthesis and map to standard cells for layout. [68]
Furthermore, the tools used by Chainworks integrate well with the existing conventional design flow. Design entry as the input to CHAINcompiler can be done using Schematic Capture or System Verilog, which in turn generates a netlist in structural Verilog. Existing tool setup can then be employed to perform synthesis and timing analysis using the scripts generated by Chainworks. [69]
5.4.1.2 Pro’s
Chainworks has the following advantages:
– Estimate of performance of corresponding circuits: Silistix claims that Chainworks leads to significant power savings compared to a conventional design flow. However, replacing the clock with handshaking signals might lead to some area overhead.
– Commercial or Non-commercial implementations: Chainworks has been used to implement "a smart card test IC built in 180-nanometer CMOS tech- nology." [70]
– Integration with Nordic Semiconductor’s design flow: According to [67], Chainworks can easily integrate into the existing synchronous design flow. It can use Verilog as an input and generate a structural netlist in Verilog.
5.4.1.3 Con’s
Chainworks has the following disadvantages:
– Longevity: Chainworks was introduced by Silistix in 2006. However, since it is not freely available, no open information or reasearch papers are available for Chainworks. Hence, it is difficult to comment on the longevity of this tool. – Tool complexity: It will take sometime for the designers to educate themselves
on how the new tool suite functions.
– Cost: It is not a freely available tool and thus there is a cost associated with this tool. Chainworks is a commercially available tool which is approximately priced the same as Synopsis Design Compiler, which is a tool for synthesizing and performing the timing analysis for synchronous design.
– Delay model used by the final netlist: This information is not available openly, and since Silistix was not contacted, it is difficult to comment on the nature of the netlist obtained from the Chainworks tool suite. However, it seems like Chainworks is following a desynchronization approach, see Section 5.5.1 on the facing page.
– Support: No separate webpage for Chainworks was found. Moreover, Chain- works was not found on the webpage for Silistix [71].
5.4.1.4 Chainworks discussion
Chainworks was eliminated and was not looked into any further. It was mainly because of the high cost and the desynchronization approach used. Desynchronization involves replacing clock domains by local handshaking circuitry. This leads to alot of overhead. It is not a purely asynchronous technique and involves conversion from a synchronous design to an asynchronous one, which is not the most efficient way available. Moreover, the aim of this thesis is to find a purely asynchronous tool.
5.4.2
ACC
ACC stands for Asynchronous Circuit Compiler. It is a commercial synthesis tool by Tiempo, that generates DI asynchronous circuits from input specifications in standard HDL such as Verilog or VHSIC Hardware Description Language (VHDL). According to Tiempo’s website [72], the licence for ACC can be purchased.
5.4.2.1 Overview
ACC takes design descriptions in Verilog/System Verilog, and generates a standard Verilog gate level netlist as the output. "ACC can be inserted in any standard design flow, allowing designer to verify asynchronous and mixed asynchronous/synchronous circuits using any industry-standard simulation tools. The generated Verilog netlist can then be placed-and-routed using any standard back-end tool and verified with any electrical simulation tool." [72]
5.4.2.2 Pro’s
ACC has the following advantages:
– Delay model used by the final netlist: The website [72] claims to generate a DI netlist. Owing to less strict timing analysis requirements, a delay DI is the most suited for the purpose of this thesis.
– Integration with Nordic Semiconductor’s design flow: ACC integrates well with the standard synchronous design tools and flow. It uses standard HDL
such as Verilog/System Verilog as the input specification language. Moreover, it produces a gate level netlist in standard Verilog format as an output. – ACC is a fully automatic synthesis tool.
5.4.2.3 Con’s
ACC has the following disadvantages:
– Cost: Being a commercial tool, there is a certain cost associated with the purchase of the ACC license.
– The website [72] seems to provide extremely general information without getting into any ACC details or specifics. Hence, a lot of parameters such as longevity, tool complexity, performance, commercial implementations and support are unknown.
5.4.2.4 ACC discussion
Based on ACC’s pro’s and con’s, ACC is one amongst the selected shortlisted tools mainly because of the DI nature of the netlist obtained and the possibility for easy integration into Nordic Semiconductor’s tool flow. Using a Verilog input and outputting a Verilog netlist is ideal for this thesis. Even though ACC had an associated cost, it appeared to be exactly something that was required. It was thought that in the next integration phase, Tiempo could be contacted for ACC, and hence, the unknown parameters could also be figured out.