Petrify

Petrify is one of the most popular academic research tools for the synthesis of asynchronous circuits. The tool uses graphical based specifications in the form of PN, STG, SG or TS as an input for synthesis. It is freely available on the web. Petri Net Markup Language (PNML) [61] is a standard format for the specification of Petri Nets.

5.2.1.1 Overview

Petrify is a well known tool for the manipulation of concurrent specifications and for synthesizing and optimizing asynchronous control circuits. "Given a Petri Net (PN), a Signal Transition Graph (STG), or a Transition System (TS) it generates another PN or STG which is simpler than the original description and produces an optimized net-list of an asynchronous controller in the target gate library while preserving the specified input-output behavior." [7] In short, from a given specification as input,

43 Petrify outputs an optimized netlist of the asynchronous circuit and a simplified PN showing the events and the various transitions between them. The latter provides the ability to back-annotate to the original specification.

Petrify transforms a specification by performing a token flow analysis of the original PN and thereby producing a TS. Initially, all the transitions having the same label are marked as one event. Then, the transitions are relabelled for fulfilling the requirements in order to obtain a safe irredundant PN and the TS is transformed. As a part of synthesis, Petrify solves various logic synthesis problems such as logic decomposition, state encoding and technology mapping onto a gate library in order to generate a netlist. The final netlist is a speed independent circuit which means that the circuit is guaranteed to be hazard free irrespective of the gate delays and changes in multiple inputs which satisfy the initial specification. Figure 5.2 shows the Petrify framework. "Petrify can also synthesize circuit under timing assumptions specified by the designer or automatically generated by the tool" [62] Petrify is a well equipped tool that can be used for PN composition, PN synthesis and re-synthesis of asynchronous control circuits and other related areas dealing with concurrent asynchronous specifications or programs. [7]

Transition System FSM CSP CCS State Graphs Petri Nets Burst-mode automata Free-choice PN

Safe Petri Net

Irredundant PN State encoded Transition System Asynchronous circuit (netlist) Gate library Model transformation Synthesis of Petri Nets

Synthesis of asynchronous circuits

Figure 5.2: Block diagram of the Petrify synthesis framework.

Based on a figure in [7]

Petrify implements a method in which a safe PN with a reachability graph similar to the original PN or TS is synthesized from an originally given PN or TS. The new

PN formed is nothing but a minimized version of the original PN. The reachability graph is said to be isomorphic to either the original PN or the minimized PN. The synthesized PN exhibits place irredundancy, which means that removing a place from the net would change its behaviour. [7]

Petrify can also be used to generate netlists in Verilog, EQN or BLIF. The process from an initial PN to the generation of a circuit netlist is completely automated. Petrify has been used for the synthesis of asynchronous controllers such as AMULET microprocessor, circuits from RAPPID by Intel Corporation and controllers based on theseus logic [20]. [32] describes a reverse engineering methodology of synthesizing PNs from state-based models such as Finite State Machine (FSM) or TS. [33] presents a method for the automated synthesis of asynchronous circuits from specifications based on process algebra. It combines PNs and process algebra for the specification and synthesis of the given asynchronous circuit.

5.2.1.2 Pro’s

Petrify has the following advantages:

– Longevity: Petrify was developed in the the late 90’s. The latest version of Petrify available on the Petrify webpage is from 1999. There is no improved or upgraded version since then. Even though, it seems like Petrify is not actively developed, the 1999 version of Petrify seems to be extremely stable since it has been the most used tool for academic research on asynchronous design. The last academic research paper [63] and book [64] found for Petrify are from 2000. However, the latest version of PNML available is from 2009 [61].

– Cost: Petrify is freely available from the Petrify webpage [30].

– Commercial or Non-commercial implementations: Even though there are no commercial implementations of Petrify, it has been the most widely used tool for academic projects in the field of asynchronous design. Petrify has been used for the synthesis of asynchronous control circuits in several projects. – Integration with Nordic Semiconductor’s design flow: Petrify can gen-

erate a netlist in Verilog which makes integration with Nordic Semiconductor’s tool chain more feasible since Verilog is the HDL being used in the Nordic Semiconductor’s design flow.

– Petrify exhibits a property of back-annotation which helps the designer to execute more control over the design process.

5.2.1.3 Con’s

45 – Tool complexity: Specification of the design in PN format is cumbersome. An in-depth understanding of PNs and PNML i.e. the language to describe PNs is required for this purpose. Understanding PNs can be time consuming and complicated.

– Estimate of performance of corresponding circuits: State space explo- sion can be a problem with Petrify for STGs involving many variables which might consume hours of CPU time. Even though Petrify is a powerful tool for logic synthesis, a more realistic approach to where it can be used efficiently is required while using it. [18]

– Delay model used by the final netlist: Petrify generates a speed-independent netlist. A speed independent netlist requires timing analysis for isochronic forks. This increases the timing validation effort.

– Support: Unknown

– For rapid implementation and synthesis using Petrify, a way has to be figured out for the conversion from standard HDL (Verilog) to PN or STG which is yet unknown. [64] has made an attempt to describe a technique doing so. However, as of now there is no specific known method or standard to convert Verilog to PN or STG.

5.2.1.4 Petrify discussion

Petrify is one amongst the selected shortlisted tools mainly because of its wide use and acknowledgement for academic research based projects in the field of asynchronous design. Moreover, some papers suggest that Petrify can generate a Verilog netlist, which was ideal for the thesis. Hence, trying out Petrify for further investigation was thought to be a good idea.