Implementation on control platform and experimental verification The predictive optimal sequence SVM has been implemented on a commercial control

platform (OPCoDe by ABB), which allows implementation of control in Matlab / Simulink, simulation of the code in that environment and direct downloading of the same code to the target application. In order to allow implementation on the CPU rather than on the FPGA, the code has been optimized for fast execution.

6.2.3.1

Modulator adaptations for implementation on control platform

The sequence length has been reduced to 3 and only single commutations are allowed. This reduced the maximum number of sequences to be calculated to 40 (5 starting states with 2 trees each, each of the trees having 4 sequences). THD calculation has been excluded to further speed up calculation. No additional optimal states are considered.

6.2.3.2

Experimental results

The optimal sequence SVM algorithm has been verified on the 6kVA 5-L ANPC prototype. Figure 101 shows one specific operating point of m = 0.9. The DC-side of the converter is supplied by a constant DC source of VDC = 80V and the AC-side terminals are connected to a three-phase RL load (10 Ω and 4.2 mH, cos(ϕ) = 0.966 at 25 Hz). The resulting current is 2.8 A.

Figure 101, Predictive optimal sequence SVM scheme with single commutations

A 9-L waveform can be seen in the measured phase to phase voltages (given by the 5-L waveform in each phase) in Figure 101. The converter is balancing the NP as expected. A 3rd harmonic is clearly visible on the graph on the left side.

6.3

Executive summary for chapter 6

This chapter has introduced NP control methods for the 5-L ANPC based on SVM making use of optimized sequences. The first approach explores the possibility of combining specific states into modified and virtual vectors having different properties than the state combinations obtained with standard modulation schemes. The existence of such vectors is based on the fact that a flying capacitor cannot only be balanced by truly redundant states, but also by a combination of states with different output voltages. Namely a suitable combination of +UDC/4 and –UDC/4 states can generate either zero NP current or a large NP current while keeping the FC balanced. For small modulation depth, such states can be applied by CM jumps without impact on the DM voltage. If the states to be combined belong to the same αβ-vector, we call them modified vectors; if the states to be combined belong to adjacent αβ-vectors (one level apart), we call them virtual vectors type 1; if they are two levels apart, we call them virtual vectors type 2.

The availability of such vectors in the whole space vector hexagon has been analyzed. All vectors are available in star shaped regions of different size as shown in Figure 90. The impact of individual modified and virtual vectors has been investigated and is shown with TABLE 48 to TABLE 50. The new vectors could be applied directly for a NTV SVM, using those vectors on the vertices of new triangles. This approach is not as straight forward as it seems, as a large number of regular, modified and virtual vectors are available for the modulation. An online selection is computationally very demanding, as a very large number of sequences are possible.

An approach with an offline determination of optimal sequences has been chosen to be implemented. This approach allows for an optimization of the switching losses while providing large NP current control capacity. The predetermined sequences can be stored in a lookup table, which contains the true discrete state to be applied; the modified and virtual vectors are hidden in those states. The modulator can therefore use the standard discrete vertices for an NTV SVM rather than the virtual vectors with differing positions. This has the advantage that no new NTV algorithms need to be developed.

The modified and virtual vector sequence scheme is very powerful. The NP control capacity is highly increased for all modulation depths and all load angles. Minimum and maximum NP currents as a function of load angle and vector position are given in TABLE 87 in the appendix. Maximum and minimum average NP current over one fundamental period are given in TABLE 88.

An alternate method for the generation of optimized vector sequences is proposed in the second part of the chapter. The sequences are determined with a standard NTV SMV, but the choice of redundant states is done with an optimal control algorithm. This approach has the advantage that several objectives can be handled with one single controller. This may include, switching losses or harmonic distortion in addition to the capacitor balancing.

The theoretical number of possible sequences is very high. The evaluation of them has to be done by full enumeration, which is computationally very demanding. Therefore, only a subset of sequences can be considered. An obvious reduction of the number of sequences can be done by a limitation of the number of commutations allowed per transition to limit the switching losses. As an inherent feature of the concept, the state combinations according to modified and virtual vector definitions can be chosen automatically. However, this is only possible if a sufficiently large number of commutations per transition are allowed to enable the CM jumps required for the virtual vector application. In practice, this could not be realized. Several thousand sequences would need to be

considered in each modulation step. Different strategies to limit the number of sequences to be included in the evaluation are presented.

Simulations show promising performance regarding output voltage distortion and loss minimization trade off. Depending on the tuning of the control parameters, one of the two optimization criteria can be significantly improved compared to PD PWM. The modulator implemented for simulation is too complex for real time execution. A simplified version has been implemented for experimental verification. Basic functionality could be demonstrated, but the control performance was below expectations due to the simplifications applied. A significant effort is still required to implement a suitable algorithm on an FPGA rather than executing it on the CPU. This task has not been tackled in the frame of this thesis and could be the subject of future work.