Incremental Timing-driven Placement Techniques

Incremental timing-driven placement techniques place a subset of the circuit netlist, re- taining the locations of a majority of the modules as obtained from the previous stage within a physical synthesis flow. They typically use a path-based approach, wherein they model the various physical properties like gate delay, interconnect delay etc., during placement, and try to directly optimize the timing critical paths in the design. Although many flavors exist, a major- ity of these techniques use the approach of linear programming [31], to perform timing-driven incremental placement.

The key drawbacks of incremental timing-driven placement techniques are:

• To perform module movement, these techniques often rely on inaccurate or crude models for the various physical properties like gate delay, interconnect delay etc. Typically, they use a linear model for the interconnect delay, which breaks down when the modules need to move by a large distance. As a result, they constrain the movement of the modules to a local region (e.g., [16, 17, 40]).

• Since incremental placement techniques rely on computationally intensive mathematical programming techniques, they are limited in their scope in terms of the number of paths that can be considered during placement. Hence, they cannot be used during the early stages of physical synthesis where a large number of paths need to be simultaneously optimized.

• As with global placement techniques, they typically do not interact with timing optimiza- tion transforms during placement. As an exception, certain techniques for considering optimization during placement have been proposed (e.g., [14]), but again, they rely on in- accurate and simple delay models that do not reflect the complexities of nanometer-scale integrated circuit design.

• Incremental timing-driven placement techniques typically ignore module overlap con- straints during the solution of the mathematical program. To resolve the overlaps among the modules, these techniques rely on a subsequent legalization step which is often timing

unaware. This can lead to a degradation in design timing as there is no guarantee for the legalization step to preserve the design timing as seen at the end of the critical path optimization step.

• The legalization issue is particularly magnified in modern designs that contain numerous fixed macros which appear as placement blockages. This results in a highly fragmented placement region in which the modules need to be placed. Incremental placement tech- niques do not explicitly model and account for placement blockages during critical path optimization.

• Finally, they do not address other placement issues like placement density constraints, which are required to provide space for timing optimization and routing. As with global placement techniques, excessive packing of modules within a local region during incre- mental placement can cause routing congestion issues.

6.2 Key Contributions of This Work

This work is motivated by the following observations: (a) a robust and high-quality timing closure flow requires a close coupling between placement and timing optimization (e.g., buffer insertion and gate sizing), and (b) both steps should rely on accurate timing information from a state-of-the-art timing analysis tool which can model the complexities of nanometer-scale VLSI design.

In this respect, this chapter describes an Integrated Timing Optimization and Placement (ITOP) algorithm to achieve timing closure on nanometer-scale VLSI designs. In contrast to existing approaches, ITOP does not rely on a net specification based timing-driven placement, or on delay modeling followed by computationally intensive mathematical programming. To achieve timing closure within a physical synthesis flow, it uses an incremental approach with tight integration between placement and timing optimization, to gradually improve design timing without degrading wire length and routability.

tion and Placement algorithm are:

• A simple, yet effective netlist transformation technique to model the critical paths in the design, so that they can be effectively optimized during placement. To identify the critical paths, this technique uses accurate timing from a timing analysis engine.

• An efficient incremental placement technique that directly optimizes critical path lengths while considering placement blockages during critical path optimization. It should be noted, none of the existing path-based approaches to timing-driven placement explicitly model placement blockages during critical path optimization.

• A tight integration of placement with incremental timing optimization, which in turn uses accurate timing information from a static timing engine to perform buffer insertion and gate sizing on the design.

• An iterative flow that includes periodic congestion mitigation, wire length recovery and slack histogram compression, to improve design timing without sacrificing total wire length and routability.

Since ITOP has been primarily developed to improve design timing during the early stages of physical synthesis (in other words, have a global impact on the design timing), it is embedded within a physical synthesis framework as shown in Figure 6.3. Please note, the incremental nature of ITOP also makes it attractive to perform fine-grained critical path optimization. Hence, it can also be employed within the detailed placement and optimization stage of physical synthesis if required (Figure 6.1).

The rest of this chapter is organized as follows: Section 6.3 provides an overview of the ITOP algorithm. This is followed by Sections 6.4 – 6.7 that describe the individual components of the algorithm in detail. Section 6.8 gives the detailed algorithm for ITOP as employed within an industrial physical synthesis framework. Experimental results on industrial designs in the 65nm and 45nm process technology nodes are reported in Section 6.9. The chapter concludes with some key observations in Section 6.10.

Initial Placement

Integrated Timing Optimization and Placement (ITOP) Coarse Timing Optimization

Clock Insertion and Optimization

Routing

Post Route Optimization Initial Placement

Integrated Timing Optimization and Placement (ITOP) Coarse Timing Optimization

Clock Insertion and Optimization

Routing

Post Route Optimization

Figure 6.3 A physical synthesis flow incorporating Integrated Timing Op- timization and Placement.