Introduction Introduction Introduction Introduction
The PCI Interface Controller complies with PCI Local Bus Specification, Revision 2.11. Both master and target capabilities are supported. The interface implements 3.3V PCI-compliant pads (5V tolerant). The PCI bus operates at 66 MHz and supports burst transfers. The PCI Interface Controller serves as a PCI bridge between the PCI bus and the RC32134 internal bus. The block diagram of the PCI Interface Controller is shown in Figure 6.1.
The PCI bus interface contains two separate data paths, one for access initiated by the CPU or DMA and one for access initiated by an external PCI agent. Each path has its own FIFO, and each one operates independently of the other. The FIFOs in the interface include:
! Bidirectional PCI master FIFO (PCI Interface Controller is PCI bus master)
! Bidirectional PCI target FIFO (PCI Interface Controller is PCI bus target)
Features Features Features Features
The PCI Interface Control Core provides the following:
! Master and Target Controllers
– Host or Satellite (Adapter Card) mode
– Configuration mechanism #1 to access configuration registers from CPU – Target lock support
! The following PCI FIFO sizes are used:
– master transmit and receive FIFOs are 8 words – target transmit and receive FIFOs are 8 words
! PCI Bus Arbitration selection in Host Mode – Internal or External arbiter
– Internal arbiter provides:
- Fixed priority or Round Robin - Arbitrate 3 external PCI masters
! Mailbox registers
! Software programmable endianness byte swapper
! Address translation between CPU address space and PCI address space
! Separate DMA engine for PCI target transfers from PCI bus to CPU memory
! Support for Plug and Play
1. For operational details and/or timing diagrams not included in this chapter, refer to the PCI 2.1 specifications.
PCI Interface Controller Functional Overview
Notes
Figure 6.1 PCI Interface Controller Block Diagram
Functional Overview Functional Overview Functional Overview Functional Overview
During reset, three reset initialization pins (mem_addr[22:20]) must be set up properly to select the desired PCI and boot modes for the RC32134. Table 6.1 shows all of the possible mode configurations with the settings of mem_addr[22-20] pins, which are latched after reset. The PCI interface controller can be in either host mode or satellite mode.
RC32134 PCI Bus Master Operation
RC32134 PCI Bus Master operation is defined as CPU or general purpose DMA initiated read/write transfers between RC32134 and PCI bus. The address map is shown in Table 6.2 when CPU or DMA wants to access the PCI bus. The CPU or DMA can read/write to targets on the PCI bus through 3 PCI memory spaces. When accessing PCI memory space, the corresponding PCI memory space Base Register (BR) translates a local physical CPU address into a PCI address by modifying the top 4 address bits of the local CPU address.
Similarly, when accessing PCI I/O space, the PCI I/O space Base Register translates a local physical CPU address into a PCI address by modifying the top 4 address bits of the local CPU address. The BRs can point to the same or overlapping address spaces, if desired. The endianness swap setting can be modi-fied for each of the BRs by setting a bit in each BR.
mem_addr[22:21] mem_addr[20] Description
0 0 0 Host mode, boot from memory controller, serial EEPROM
not supported
0 0 1 Satellite mode, boot from memory controller, serial
EEPROM not supported
0 1 1 Reserved
1 0 Don’t care Reserved
1 1 Don’t care RC32134 idle at reset
Table 6.1 Initialization Pins mem_addr[22:20] Settings
Memory RC32364 CPU Bus Internal Bus
(IDT Peripheral Bus)
PCI Interface Controller PCI Bus
PCI Target Receive FIFO
PCI Interface Controller Functional Overview
Notes
RC32134 PCI Bus Target Operation
RC32134 PCI Bus Target operation is defined as PCI bus external master initiated read/write transfers between the PCI bus and CPU memory, or between the PCI bus and an external I/O. Note that only 32-bit width memory on the CPU bus is supported. The PCI bus master can read/write to memory through a CPU memory space 1 BR. The CPU memory space 1 BR translates a PCI address to a local physical CPU address by modifying the top 4 address bits of the PCI address. The size of the memory space accessed from the PCI bus is 256MB.
The PCI controller uses a dedicated DMA engine, separate from the four general purpose DMA controller channels in Chapter 7, to initiate PCI bus target transfers to and from CPU bus memory.
Similarly, when accessing I/O, the CPU I/O space BR translates a PCI address to a local physical CPU address by modifying the top 4 address bits of the PCI address. Note that only the 8 address bits of the PCI address bus are used, for I/O access, as the I/O space accessed from the PCI bus is limited to 64 words (256 bytes). The BRs can point to the same or overlapping address spaces if desired and can point also to RC32134 registers, if desired. The endianness swap setting can be modified for each of the above BRs by setting a bit in each BR.
The RC32134 PCI Bus Target supports PCI bus access to 8-/16-/32-bit external I/O, assuming the I/O addresses are aligned on a word boundary and the data are in the correct 1/2/4 byte lanes. Note there is NO byte unpacking and the remainder of the word will not be used if it is an 8-/16-bit external I/O access.
When the RC32134 PCI is a target, external PCI masters can only perform single word PCI I/O accesses (either read or write). When the RC32134 PCI is a master, it can perform quad-word burst PCI I/O accesses (either read or write).
Burst transfers for memory space are fully supported by the RC32134 integrated processor, when it is configured as a PCI master or as a target.
The RC32134 PCI does not support the cache line wrap mode defined in the PCI specification. Thus, the RC32134 PCI master never generates a cache line wrap mode. A cache line wrap mode cannot be generated from PCI agents, since the RC32134 does not recognize this mode. If this mode were generated from the PCI bus, the RC32134 would treat this access as linear incrementing.
The RC32134 PCI controller supports lock accesses when RC32134 is a PCI target. However, the lock accesses cannot be issued when the RC32134 is a PCI master.
PCI Commands Supported
The RC32134 PCI master supports PCI memory read line and memory write invalidate commands.
Memory read line performs a quad-word burst read and memory write invalidate performs a quad-word write. To enable the memory write invalidate command, the cache line size in the configuration register must be nonzero, and the memory write and invalidate enable bit in the command configuration register must be enabled. As a PCI target, RC32134 supports memory read line, memory read multiple, and memory write invalidate.
From To Allocation
1800_2000 1800_2FFF PCI Internal Registers (4KB) 1880_0000 188F_FFFF PCI I/O Space (1M)
18C0_0000 18FF_FFFF PCI Memory Space 3 (4MB) (for non-PCI boot reset option) 1FC0_0000 1FFF_FFFF PCI Memory Space 3 (4MB) (for boot from PCI bus option) 4000_0000 5FFF_FFFF PCI Memory Space 1 (512MB)
6000_0000 7FFF_FFFF PCI Memory Space 2 (512MB) Table 6.2 PCI Address Map
PCI Interface Controller Functional Overview
Notes
Table 6.3 summarizes the PCI command codes supported (and not supported) by the controller as master and as target.PCI Configuration Register Access
The way RC32134 interfaces and accesses the configuration registers is defined in the PCI specification 2.1, Section 3.7.4.1, Configuration mechanism #1. This mechanism requires the following two RC32134 internal registers be defined to access PCI configuration space:
! PCI Configuration Address Register at 1800_2cf8
! PCI Configuration Data Register at 1800_2cfc.
When accessing a PCI configuration register, first write the desired address of configuration register to PCI Configuration Address register, and then read (or write) the PCI Configuration Data register to receive (or to send) data. The data in the PCI Configuration Data register will be automatically sent to (or received from) the desired configuration register.
Before the RC32134 can be ready to perform any PCI operations, its PCI configuration registers must be set up correctly. The RC32134 PCI master and target are defaulted to not ready (disabled) after reset.
If the RC32134 PCI is in host mode, then the CPU needs to configure the RC32134 PCI configuration registers, including read-only configuration registers. The RC32134 PCI target is not ready until the PCI target not ready bit (bit 2 of the PCI arbitration register) is set to 0. When the RC32134 PCI target is not ready, all the PCI assesses to RC32134 from the PCI bus will be retried by the PCI controller. Thus, after the writing of configuration registers is complete and RC32134 is ready, bit 2 of the arbitration register needs to be set to 0 to enable the RC32134 PCI target operations.
If the RC32134 PCI is in satellite mode, read-only configuration registers can be loaded by the CPU. If the CPU finishes loading the read-only configuration registers in the satellite mode, then bit 2 of the PCI arbitration register needs to be set to 0, so that the RC32134 PCI target can respond to accesses from the PCI bus. If the boot mode initialization chooses to use the EEPROM to load read-only configuration regis-ters, then the system using the RC32134 must be booted from the PCI bus after reset.
CBEn[3:0] Command As a Master As a Target
0000 Interrupt Acknowledge No Ignored
0001 Special cycle No Ignored
0010 I/O read Yes Yes
0011 I/O write Yes Yes
010x Reserved
0110 Memory read Yes Yes, prefetch 4 words
0111 Memory write Yes Yes
100x Reserved
1010 Configuration read Yes Yes
1011 Configuration write Yes Yes
1100 Memory read multiple No Yes, prefetch 8 words
1101 Dual address cycle No Ignored
1110 Memory read line Yes, quad word burst read Yes, aliased to memory read 1111 Memory write and invalidate Yes, quad word burst write Yes, aliased to memory write
Table 6.3 PCI Commands
PCI Interface Controller Signal Definitions
Notes
The boot EEPROM uses 16-bit data. The PCI boot EEPROM interface reads each 16-bit half word linearly from address 00h through 42h, with each address corresponding to the internal PCI configuration space registers as defined in Table 6.14 RC32134 PCI Configuration Registers.To enable RC32134 PCI master operation, the enable bus master bit in the configuration command register must be set to 1 by the CPU if the RC32134 PCI is in host mode or by an external PCI host if in the satellite mode.
PCI Interrupts
If the PCI bus writes a 1 to one of the low order 4 bits in the PCI_to_CPU mailbox pending register, then a corresponding interrupt is generated to the CPU via the cpu_int_n[3] pin and the CPU must service and clear this interrupt. If the CPU writes a 1 to one of the low order 4 bits in the CPU_to_PCI pending mailbox register, then a corresponding interrupt is generated to the PCI bus via the pci_inta__n pin, and this inter-rupt needs to be cleared from the PCI bus. Note that the PCI_to_CPU mailbox interinter-rupt can be generated in either host or satellite mode, while CPU_to_PCI mailbox interrupts can be generated only in the satellite mode.
The CPU or DMA can initiate a PCI access and know whether it is failed or not by enabling both the PCI master read error interrupt and the PCI master write error interrupt defined in the PCI controller interrupt pending register. Note that both interrupts must be enabled to ensure that a RC32134 PCI master access error can be observed. If only one of the interrupts is enabled, then a master access error may not be detected.
To enable any PCI address or data parity error detection by the PCI interface controller, both the parity error response bit and SERR# enable bit must be enabled in the command configuration register. Two kinds of parity errors can be reported to the CPU by using two specific interrupts. These two errors are PCI Target Write Data Parity Error, and PI Master Data Parity Error, as indicated in the PCI controller interrupt pending register.