Reset Initialization and Special Modes Reset Initialization and Special Modes Reset Initialization and Special Modes
Boot software is expected to cycle 8 refreshes, before first accessing EDODRAM. The refresh counter can be set to a small value for this purpose and then set to its normal value after the reset sequence has occurred. Refresh requires WE to be high and thus a dedicated WE pin, edodram_we_n, is provided for EDODRAM hidden refreshes.
Error Recovery
The EDODRAM Controller is required to abort gracefully on a bus error and bus time-out. Both bus errors and bus time-outs latch the present physical address into the BusError Address Register. This implies that the bus error controller can only assert buserror_n up until the first ack_n would be returned.
Both ack_n and busreq_n are de-asserted when buserror_n is asserted, such that the user can connect retry_n instead of buserror_n, if desired.
On a bus error, the memory controller must skip to the transaction end state of the primary state machine and return all outputs to their transaction end values. A bus time-out may occur at any time during the bus transaction, even after the first ack_n has been returned. If the time-out occurs, then ack_n is immediately returned and the transaction continues.
External SYSWait Behavior
! READS: Sys_wait_n has to be asserted one cycle before the first expected cpu_ack_n. Acknowl-edge is asserted on the clock Acknowl-edge immediately after the CAS cycle, when edodram_cas_n[] asserts back high. Therefore, sys_wait_n should be asserted on the clock before the CAS cycle de-asserts high and kept asserted as long as the user wants to keep data valid.
! WRITE: Sys_wait_n must be asserted before the clock edge that CAS cycle first asserts, or it will be ignored. This is because write data is latched using “early write” timing on the asserting edge of edodram_cas_n[] going low.
EDODRAM Controller Register Definitions
Notes Register Definitions Register Definitions Register Definitions Register Definitions
The Base Address and Base Mask registers allow selection of the address range to be decoded for each channel. The address mapping for these registers is provided in Table 5.4. Programming of the EDO Control Register fields shown in Figure 5.2 enables the device’s features as described in Figure 5.2 on page 5-4.
EDODRAM Control Register
Figure 5.2 EDODRAM Control Register Fields Base
Address Register Name Offset
Address Effective
Address
1800_0000
DRAM Base Address Register Bank0 C0 Base + offset DRAM Base Mask Register Bank0 C4
DRAM Base Address Register Bank1 C8 DRAM Base Mask Register Bank1 CC DRAM Base Address Register Bank2 D0 DRAM Base Mask Register Bank2 D4 DRAM Base Address Register Bank3 D8 DRAM Base Mask Register Bank3 DC
EDODRAM Control Register 310
Table 5.4 EDODRAM Register Mapping
Bit Field Name Description
31 EDODRAM Enable
30:12 Reserved 11:10 EDODRAM RAS
Width Selection
This field determines the number of row addresses to compare in page mode.
Table 5.5 EDODRAM Control Register Field Descriptions (Part 1 of 2)
EDODRAM
Enable RAS Precharge Staggered Refresh RAS Wait 0
Time, tRP RAS Pulse Width,
. (refresh only)
tRAS Enable
Row address width selection for page comparator Reserved RAS Width 0 EDODRAM Controller disabled (default)
Value Description 3 12-bit Row Address 2 11-bit Row Address 1 10-bit Row Address (default) 0 9-bit Row Address
EDODRAM Controller Register Definitions
Notes
9:8 EDODRAM RAS Mux Control
Shifts the RAS Address to MemAddr bit assignments.
7:6 EDODRAM RAS
1 = Stagger bank pair [1:0] refresh from bank pair [3:2] (default) 0 = Refresh all banks at the same time
2 RAS-Asserted (page mode)
Leaving RAS asserted at the end of a DRAM transfer improves throughput by about 3 - 5%—if the next access is on the same DRAM page—by eliminating the RAS stage of subsequent transfers (up to 3 clocks saved).
However, leaving RAS asserted consumes more power and in some cases can reduce throughput, because a page miss causes a precharge penalty.
1 EDODRAM Wait Enable
1 = Enable external mem_wait_n pin for EDODRAM 0 = Disable external mem_wait_n pin for EDODRAM (default)
0 Reserved Set to 0
Bit Field Name Description
Table 5.5 EDODRAM Control Register Field Descriptions (Part 2 of 2) Value Description
3 No shift (11-bit CAS) 2 Shift 1 (10-bit CAS)
0 Reserved (don’t use)
Value Description
3 3 clocks
2 2 clocks (default)
1 1 clock
0 Reserved (don’t use)
Value Description
1 RAS left asserted at the end of each access
0 RAS enters precharge stage at the end of each access (default)
EDODRAM Controller Timing Diagrams
Notes Timing Diagrams Timing Diagrams Timing Diagrams Timing Diagrams
Figure 5.3 shows an EDODRAM non-page single word read as occurs after the EDODRAM controller has been idle, for instance after reset, refresh, or if the page mode is turned off. No precharge occurs, the row address is strobed, then the column addresses are strobed.
Note that the row to col time and the col to col time are fixed, such that sufficiently fast EDODRAM chips must be selected to match the RC32134 bus speed. When edodram_cas_n de-asserts after the datum, the extended data out characteristic of the EDODRAM chips holds the datum valid until cpu_ack_n occurs a clock later. In this example, RAS-Asserted has not been programmed, such that edodram_ras_n[x] returns high at the end of the transaction. (En=1, Width=1, Mux=2, RAS=4 clks, RP=2, StagRef=1, RAS-A=0, Wait=0).
Figure 5.3 Non-Page Word Read
Addr Data
"00"
"0000"
Row Col
Addr clk
cpu_ale cpu_ad[31:0]
cpu_wr_n cpu_ack_n cpu_addr[3:2]
cpu_be_n[3:0]
cpu_cip_n cpu_last_n edodram_addr[15:2]
edodram_ras_n[x]
edodram_cas_n[3:0]
edodram_oe_n edodram_we_n edodram_wait_n edodram_245_oe_n edodram_245_dt_r_n
Tsw1
Tdo13
Tdoh5
Tdo14
Tdo12
EDODRAM Controller Timing Diagrams
Notes
Figure 5.4 shows an EDODRAM non-page single word write, as occurs after the EDODRAM controller has been idle such as after reset, refresh, or if the page mode is turned off. Because no precharge occurs, the row address is strobed, then the column addresses are strobed. Note that the row to col time and the col to col time are fixed, such that sufficiently fast EDODRAM chips must be selected to match the RC32134 bus speed.Note that the data matches the column address timing, such that an early write on edodram_cas_n[]
asserting low occurs. In this example, RAS-Asserted has not been programmed, such that edodram_ras_n[x] returns high at the end of the transaction. (En=1, Width=1, Mux=2, RAS=4 clks, RP=3, StagRef=1, RAS-A=0, Wait=0).
Figure 5.4 Non-Page Word Write
Addr Data
"00"
"0000"
Row Col
clk cpu_ale cpu_ad[31:0]
cpu_wr_n cpu_ack_n cpu_addr[3:2]
cpu_be_n[3:0]
cpu_cip_n cpu_last_n edodram_addr[15:2]
edodram_ras_n[x]
edodram_cas_n[3:0]
edodram_oe_n edodram_we_n edodram_wait_n edodram_245_oe_n edodram_245_dt_r_n
Thld1
EDODRAM Controller Timing Diagrams
Notes
Figure 5.5 shows an EDODRAM non-page burst read, as occurs after the EDODRAM controller has been idle such as after a reset, refresh, or if the page mode is turned off. Because no precharge occurs, the row address is strobed, then the column addresses are strobed.Note that the row to col time and the col to col time are fixed, such that sufficiently fast EDODRAM chips must be selected to match the RC32134 bus speed. When edodram_cas_n de-asserts after each data, the extended data out characteristic of the EDODRAM chips holds the data valid until cpu_ack_n occurs a clock later. In this example, RAS-Asserted has not been programmed, such that edodram_ras_n[x] returns high at the end of the transaction. (En=1, Width=1, Mux=2, RAS=4 clks, RP=3, StagRef=1, RAS-A=0, Wait=0).
Figure 5.5 Non-Page Burst Read
Addr Data0 Data1 Data2 Data3
"00" "01" "10" "11"
"0000"
Row Col0 Col1 Col2 Col3
clk cpu_ale cpu_ad[31:0]
cpu_wr_n cpu_ack_n cpu_addr[3:2]
cpu_be_n[3:0]
cpu_cip_n cpu_last_n edodram_addr[15:2]
edodram_ras_n[x]
edodram_cas_n[3:0]
edodram_oe_n edodram_we_n edodram_wait_n edodram_245_oe_n edodram_245_dt_r_n
EDODRAM Controller Timing Diagrams
Notes
Figure 5.6 shows an EDODRAM non-page burst write, as occurs after the EDODRAM controller has been idle, for instance after reset, refresh, or if the page mode is turned off. No precharge occurs, the row address is strobed, then the column addresses are strobed. Note that the row to col time and the col to col time are fixed, such that sufficiently fast EDODRAM chips must be selected to match the RC32134 bus speed.Note that each datum matches the column address timing, such that early writes on edodram_cas_n[]
asserting low occur. In this example, RAS-Asserted has not been programmed, such that edodram_ras_n[x] returns high at the end of the transaction. (En=1, Width=1, Mux=2, RAS=4 clks, RP=3, StagRef=1, RAS-A=0, Wait=0).
Figure 5.6 Non-Page Burst Write
Addr Data0 Data1 Data2 Data3
"00" "01" "10" "11"
"0000"
Row Col0 Col1 Col2 Col3
clk cpu_ale cpu_ad[31:0]
cpu_wr_n cpu_ack_n cpu_addr[3:2]
cpu_be_n[3:0]
cpu_cip_n cpu_last_n edodram_addr[15:2]
edodram_ras_n[x]
edodram_cas_n[3:0]
edodram_oe_n edodram_we_n edodram_wait_n edodram_245_oe_n edodram_245_dt_r_n
EDODRAM Controller Timing Diagrams
Notes
Figure 5.7 shows an EDODRAM page-hit single word read, as occurs after the EDODRAM controller has left RAS-Asserted in page mode. In this example, EDODRAM controller matches the current page address with the previous page address and thus no precharge occurs, nor does a row address strobe.Then the column address is strobed.
Note that the row to col time and the col to col time are fixed, such that sufficiently fast EDODRAM chips must be selected to match the RC32134 bus speed. When edodram_cas_n de-asserts after the data, the extended data out characteristic of the EDODRAM chips holds the data valid until cpu_ack_n occurs a clock later. In this example, RAS-Asserted has been programmed, such that edodram_ras_n[x] remains low at the end of the transaction. In this example, the BIU Address Latch Timing Register has the DRAM decode time set to delay by 1 clock. (En=1, Width=1, Mux=2, RAS=4 clks, RP=2, StagRef=1, RAS-A=0, Wait=0).
Figure 5.7 Page-Hit Single Word Read
Extra cycle due to address latch timing at 75Mhz Extra cycle due to address latch timing at 75Mhz
Addr Data
"00"
"0000"
Col
Addr clk
cpu_ale cpu_ad[31:0]
cpu_wr_n cpu_ack_n cpu_addr[3:2]
cpu_be_n[3:0]
cpu_cip_n cpu_last_n edodram_addr[15:2]
edodram_ras_n[x]
edodram_cas_n[3:0]
edodram_oe_n edodram_we_n edodram_wait_n edodram_245_oe_n edodram_245_dt_r_n
EDODRAM Controller Timing Diagrams
Notes
Figure 5.8 shows an EDODRAM page-hit single word write as occurs, after the EDODRAM controller has left RAS-Asserted in page mode. In this example, the EDODRAM controller matches the current page address with the previous page address and thus no precharge occurs, nor does a row address strobe.Then the column address is strobed.
Note that the row to col time and the col to col time are fixed, and as such sufficiently fast EDODRAM chips must be selected to match the RC32134 bus speed. Note that the data matches the column address timing, such that an early write on edodram_cas_n[] asserting low occurs. In this example, RAS-Asserted has been programmed, such that edodram_ras_n[x] remains low at the end of the transaction. (En=1, Width=1, Mux=2, RAS=4 clks, RP=3, StagRef=1, RAS-A=1, Wait=0).
Figure 5.8 Page-Hit Single Word Write
Addr Data
"00"
"0000"
Row Col
clk cpu_ale cpu_ad[31:0]
cpu_wr_n cpu_ack_n cpu_addr[3:2]
cpu_be_n[3:0]
cpu_cip_n cpu_last_n edodram_addr[15:2]
edodram_ras_n[x]
edodram_cas_n[3:0]
edodram_oe_n edodram_we_n edodram_wait_n edodram_245_oe_n edodram_245_dt_r_n
EDODRAM Controller Timing Diagrams
Notes
Figure 5.9 shows an EDODRAM page-hit burst write, as occurs after the EDODRAM controller has left RAS-Asserted in page mode. In this example, the EDODRAM controller matches the current page address with the previous page address and thus no precharge occurs, nor does a row address strobe. Then the column addresses are strobed.Note that the row to col time and the col to col time are fixed, such that sufficiently fast EDODRAM chips must be selected to match the RC32134 bus speed. Note that each datum matches the column address timing, such that early writes on edodram_cas_n[] asserting low occur. In this example, RAS-Asserted has been programmed, such that edodram_ras_n[x] remains low at the end of the transaction. (En=1, Width=1, Mux=2, RAS=4 clks, RP=3, StagRef=1, RAS-A=1, Wait=0).
Figure 5.9 Page-Hit Burst Write
Extra cycle due to address latch timing at 75Mhz Extra cycle due to address latch timing at 75Mhz
Addr Data0 Data1 Data2 Data3
"00" "01" "10" "11"
"0000"
Col0 Col1 Col2 Col3
clk cpu_ale cpu_ad[31:0]
cpu_wr_n cpu_ack_n cpu_addr[3:2]
cpu_be_n[3:0]
cpu_cip_n cpu_last_n edodram_addr[15:2]
edodram_ras_n[x]
edodram_cas_n[3:0]
edodram_oe_n edodram_we_n edodram_wait_n edodram_245_oe_n edodram_245_dt_r_n
EDODRAM Controller Timing Diagrams
Notes
Figure 5.10 shows an EDODRAM page-hit burst read as occurs after the EDODRAM controller has left RAS-Asserted in page mode. In this example, the EDODRAM controller matches the current page address with the previous page address and thus no precharge occurs, nor does a row address strobe. Then the column addresses are strobed.Note that the row to col time and the col to col time are fixed, such that sufficiently fast EDODRAM chips must be selected to match the RC32134 bus speed. When edodram_cas_n de-asserts after each datum, the extended data out characteristic of the EDODRAM chips holds the datum valid until cpu_ack_n occurs a clock later. In this example, RAS-Asserted has been programmed, such that edodram_ras_n[x] remains low at the end of the transaction. (En=1, Width=1, Mux=2, RAS=4 clks, RP=3, StagRef=1, RAS-A=1, Wait=0).
Figure 5.10 Page-Mode Burst Read
Extra cycle due to address latch timing at 75Mhz Extra cycle due to address latch timing at 75Mhz
Addr Data0 Data1 Data2 Data3
"00" "01" "10" "11"
"0000"
Col0 Col1 Col2 Col3
clk cpu_ale cpu_ad[31:0]
cpu_wr_n cpu_ack_n cpu_addr[3:2]
cpu_be_n[3:0]
cpu_cip_n cpu_last_n edodram_addr[15:2]
edodram_ras_n[x]
edodram_cas_n[3:0]
edodram_oe_n edodram_we_n edodram_wait_n edodram_245_oe_n edodram_245_dt_r_n
EDODRAM Controller Timing Diagrams
Notes
Figure 5.11 shows an EDODRAM page-miss single word read, as occurs after the EDODRAM controller has left RAS-Asserted in page mode. In this example, the EDODRAM controller does not match the current page address with the previous page address and thus a precharge of the programmed EDODRAM Precharge time of 3 clocks occurs. The row address is then strobed, followed by the column address.Note that the row to col time and the col to col time are fixed, such that sufficiently fast EDODRAM chips must be selected to match the RC32134 bus speed. When edodram_cas_n de-asserts after the data, the extended data out characteristic of the EDODRAM chips holds the data valid until cpu_ack_n occurs a clock later. In this example, RAS-Asserted has been programmed, such that edodram_ras_n[x] remains low at the end of the transaction. (En=1, Width=1, Mux=2, RAS=4 clks, RP=3, StagRef=1, RAS-A=1, Wait=0).
Figure 5.11 Page-Miss Single Word Read
Figure 5.12 shows a 5 clock CAS-beforeRAS EDODRAM refresh with the Staggered Refresh field mode turned off. edodram_ras_n[3:0] asserts for 4 clocks. After the refresh, the edodram_ras_n signals return de-asserted for at least the RP precharge time (not shown). (En=1, Width=1, Mux=2, RAS=4 clks, RP=3, StagRef=1, RAS-A=1, Wait=0).
Figure 5.12 Non-Staggered EDODRAM Refresh
tRP tRP
Extra cycle due to address latch timing at 75 Mhz Extra cycle due to address latch timing at 75 Mhz
Addr Data
EDODRAM Controller Timing Diagrams
Notes
Figure 5.13 shows a 10 clock cas-before-ras EDODRAM refresh with the Staggered Refresh field mode turned on. edodram_ras_n[2,0] asserts for 4 clocks and then edo_ras_n[3,1] asserts for 4 clocks. After the refresh, the edodram_ras_n signals return de-asserted for at least the RP precharge time (not shown).(En=1, Width=1, Mux=2, RAS=4 clks, RP=3, StagRef=0, RAS-A=0, Wait=0).
Figure 5.13 Staggered EDODRAM Refresh
F A F 5 F
F 0 F 0 F
clk edodram_ras_n[3:0]
edodram_cas_n[3:0]
edodram_oe_n edodram_we_n
EDODRAM Controller Timing Diagrams
Notes
Notes
Chapter 6