Interrupt Definitions

The following sections describe interrupts as they are implemented on the e200z3.

4.6.1

Critical Input Interrupt (IVOR0)

A critical input exception is signaled to the processor by the assertion of the critical interrupt pin

(p_critint_b). When the e200z3 detects the exception, if critical interrupts are enabled (MSR[CE] = 1), the e200z3 takes the critical input interrupt. The p_critint_b input is a level-sensitive signal expected to remain asserted until the e200z3 acknowledges the interrupt. If p_critint_b is negated early, recognition of the interrupt request is not guaranteed. After the e200z3 begins execution of the critical interrupt handler, the system can safely negate p_critint_b.

A critical input interrupt may be delayed by other higher priority exceptions or if MSR[CE] is cleared when the exception occurs.

Table 4-9 lists register settings when a critical input interrupt is taken.

IVOR11 411 Fixed-interval timer interrupt

IVOR12 412 Watchdog timer interrupt

IVOR13 413 Data TLB error

IVOR14 414 Instruction TLB error

IVOR15 415 Debug

IVOR16–IVOR31 — Reserved for future architectural use -Specific IVORs (Defined by the EIS)

IVOR32 528 SPE APU unavailable

IVOR33 529 SPE floating-point data exception

IVOR34 530 SPE floating-point round exception

Table 4-9. Critical Input Interrupt Register Settings

Register Setting Description

CSRR0 Set to the effective address of the instruction that the processor would have attempted to execute next if no exception conditions were present.

CSRR1 Set to the contents of the MSR at the time of the interrupt.

MSR UCLE 0 SPE 0 WE 0 CE 0 EE 0 PR 0 FP 0 ME — FE0 0 DE —/01 FE1 0 IS 0 DS 0 RI 02 ESR Unchanged

Table 4-8. IVOR Assignments (continued)

When the debug APU is enabled, MSR[DE] is not automatically cleared by a critical input interrupt but can be configured to be cleared through HID0 (HID0[CICLRDE]). Refer to Section 2.13.1, “Hardware Implementation-Dependent Register 0 (HID0).”

IVOR0 is the vector offset register used by autovectored critical input interrupts to determine the interrupt handler location. The e200z3 also provides the capability to directly vector critical input interrupts to multiple handlers by allowing a critical input interrupt request to be accompanied by a vector offset. The

p_voffset[0:11] inputs are used in place of the value in IVOR0 to form the interrupt vector when a critical

input interrupt request is not autovectored (p_avec_b negated when p_critint_b asserted).

4.6.2

Machine Check Interrupt (IVOR1)

The e200z3 implements the machine check exception as defined in Book E except for automatic clearing of MSR[DE]. The e200z3 initiates a machine check interrupt if MSR[ME]=1 and any of the machine check sources listed in Table 4-2 is detected. As defined in Book E, the interrupt is not taken if MSR[ME] is cleared, in which case the processor generates an internal checkstop condition and enters checkstop state. When a processor is in checkstop state, instruction processing is suspended and generally cannot continue without restarting the processor. Note that other conditions may lead to the checkstop condition; the disabled machine check exception is only one of these.

The e200z3 implements MCSR to record the sources of machine checks. See Section 4.4.1, “Machine

Check Syndrome Register (MCSR),” for more information.

MSR[DE] is not automatically cleared by a machine check exception but can be configured to be cleared or left unchanged through HID0[MCCLRDE]. See Section 2.13.1, “Hardware Implementation-Dependent Register 0 (HID0).”

4.6.2.1 Machine Check Interrupt Enabled (MSR[ME]=1)

Machine check interrupts are enabled when MSR[ME]=1. When a machine check interrupt is taken, registers are updated as shown in Table 4-10.

MCSR Unchanged DEAR Unchanged

Vector IVPR[32–47] || IVOR0[48–59] || 0b0000 (autovectored) IVPR[32–47] || p_voffset[0:11] || 0b0000 (non-autovectored)

1 _{DE is cleared when the debug APU is disabled. Clearing of DE is optionally supported by control in HID0 when the debug APU} is enabled.

2 _{RI is cleared by all critical class interrupts using CSRR0/1 and the machine check interrupt. These interrupt handlers} should set RI early in the handler after CSRR0/1 have been saved to allow for improved recoverability.

Table 4-9. Critical Input Interrupt Register Settings (continued)

The machine check input, p_mcp_b, can be masked by HID0[EMCP].

Most machine check exceptions are unrecoverable in the sense that execution cannot resume in the context that existed before the interrupt. However, system software can use the machine check interrupt handler to try to identify and recover from the machine check condition. In particular, the MCSR is provided to identify the sources of a machine check and may be used to identify recoverable events.

The interrupt handler should set MSR[ME] as early as possible to avoid entering checkstop state if another machine check condition occurs.

4.6.2.2 Checkstop State

The following exception conditions can cause a checkstop if MSR[ME]=0: • A machine check occurs (other than a non-maskable interrupt).

• First instruction in an interrupt handler cannot be executed due to a translation miss (ITLB), a page marked no execute (ISI), or a bus error termination.

• Bus error termination for a buffered store .

• Precise external termination error occurs and MSR[EE]=0. Non-exception–related checkstop conditions are as follows:

• TCR[WRC]—Watchdog reset control bits set to checkstop on second watchdog timer overflow event

Table 4-10. Machine Check Interrupt Register Settings

Register Setting Description

CSRR0 On a best-effort basis, the e200z3 sets this to the address of some instruction that was executing or about to be executing when the machine check condition occurred.

CSRR1 Set to the contents of the MSR at the time of the interrupt MSR UCLE 0 SPE 0 WE 0 CE 0 EE 0 PR 0 FP 0 ME 0 DE 01 FE1 0 IS 0 DS 0 RI 02

1 _{Cleared when the debug APU is disabled. Clearing of DE is optionally supported by control in HID0 when the debug} APU is enabled.

2 _{RI is cleared by all critical class interrupts using CSRR0/1 and the machine check interrupt. These interrupt} handlers should set RI early in the handler after CSRR0/1 have been saved to allow for improved recoverability. ESR Unchanged

MCSR Updated to reflect the sources of a machine check

DEAR Unchanged unless machine check is due to a data access causing a cache parity error to be signaled; updated with data access effective address in that case