Register Set

Figure 1-3 shows the e200z3 and e200z335 register set, indicating which registers are accessible in

supervisor mode and which are accessible in user mode. The number to the left of the special-purpose registers (SPRs) is the decimal number used in the instruction syntax to access the register. (For example, the integer exception register (XER) is SPR 1.)

GPRs are accessed through instruction operands. Access to other registers can be explicit (by using instructions for that purpose such as the Move To Special Purpose Register (mtspr) and Move From Special Purpose Register (mfspr) instructions) or implicit as part of the execution of an instruction. Some registers are accessed both explicitly and implicitly.

User-Level Registers

General-Purpose Registers Instruction-Accessible Registers User General SPR (Read/Write)

0 31 32 63 0 31 32 63 32 63

User SPR general 0 (upper) GPR01 (lower)

1 _{The 64-bit GPR registers are accessed by the SPE as separate 32-bit registers by SPE instructions. Only SPE vector instructions can access the upper word.}

General- purpose registers

CR Condition register spr 256 USPRG02

2 _{USPRG0 is a separate physical register from SPRG0.}

GPR1

spr 9 CTR Count register General SPRs (Read-Only) GPR2

• • • _{spr 8 LR Link register spr 260 SPRG4}

SPR general registers 4–7

GPR31 spr 261 SPRG5

spr 1 XER Integer exception

register _{spr 262 SPRG6} L1 Cache (Read-Only)

spr 512 SPEFSCR3

3 _{EIS–specific registers; not part of the Power ISA.}

SP/embedded FP status/control register spr 263 SPRG7 L1 cache configuration register 0 spr 515 L1CFG03

ACC3 _{Accumulator Time-Base Registers (Read-Only)}

spr 268 TBL _{Time base} lower/upper spr 269 TBU

Supervisor-Level Registers

Interrupt Registers Configuration Registers

32 63 32 63 32 63

spr 63 IVPR Interrupt vector

prefix register spr 400 IVOR0

Interrupt vector offset registers 0–154

4 _{IVOR9 (handles auxiliary processor unavailable interrupt) is defined by the EIS but not supported by the e200z335.}

MSR Machine state register spr 401 IVOR1 spr 26 SRR0 _Save/restore registers 0/1 spr 1023 SVR3 System version register • • • spr 27 SRR1

spr 415 IVOR15 spr 286 PIR Processor ID register spr 58 CSRR0

Critical SRR 0/1 spr 528 IVOR323 Processor version _register

Interrupt vector offset registers 32–34 spr 287 PVR spr 59 CSRR1 spr 529 IVOR333 spr 574 DSRR03 _{Debug interrupt} SRR 0/1 spr 530 IVOR343 Timer/Decrementer Registers spr 575 DSRR13 Exception syndrome register spr 22 DEC Decrementer spr 62 ESR MMU Control and Status (Read/Write)

Decrementer auto-reload register MMU control and status

register 0

spr 54 DECAR spr 572 MCSR3 Machine check

syndrome register spr 1012 MMUCSR0

3

spr 284 TBL _{Time base} lower/upper spr 61 DEAR Data exception

address register spr 624 MAS0

3

MMU assist registers 0–4 and 6

spr 285 TBU spr 625 MAS13

Debug Registers5 spr 626 MAS23 spr 340 TCR Timer control register spr 627 MAS33

spr 308 DBCR0

Debug control registers 0–3

spr 336 TSR Timer status register spr 628 MAS43

spr 309 DBCR1

spr 630 MAS63 Miscellaneous Registers spr 310 DBCR2

Process ID register 0

spr 561 DBCR3 spr 48 PID0 spr 1008 HID03 Hardware

implementation dependent 0–1 spr 1009 HID13

spr 304 DBSR Debug status register MMU Control and Status (Read Only)

spr 1013 BUCSR6 Branch control and status register spr 562 DBCNT 6 Debug count register spr 1015 MMUCFG3 MMU configuration

spr 272–279 SPRG0–7 General SPRs 0–7 spr 312 IAC1 Instruction address compare registers 1–4 spr 688 TLB0CFG3 TLB configuration 0/1

spr 313 IAC2 spr 689 TLB1CFG3 Context Control (Read/Write)

spr 314 IAC3 _{Context control}

register Parallel Signature Unit Registers6 spr 560 CTXCR6

spr 315 IAC4 Data address compare registers 1 and 2 dcr 272 PSCR PS control spr 316 DAC1 dcr 273 PSSR PS status spr 317 DAC2 dcr 274 PSHR PS high spr 318 DVC1 Data value dcr 275 PSLR PS low

compare

spr 319 DVC2 registers 1 and 2 dcr 276 PSCTR PS counter dcr 277 PSUHR PS update high dcr 278 PSULR PS update low

Figure 1-3. e200z3 Programmer’s Model

1.3

Instruction Set

The e200z3 implements the following instructions:

• The Power ISA instruction set for 32-bit embedded implementations. This is composed primarily of the user-level instructions defined by the user instruction set architecture (UISA). The e200z3 does not include the Power ISA floating-point, load string, or store string instructions.

• The e200z3 supports the following EIS-defined instructions:

— Integer select category. This category consists of the Integer Select instruction (isel), which functions as an if-then-else statement that selects between two source registers by comparison to a CR bit. This instruction eliminates conditional branches, takes fewer clock cycles than the equivalent coding, and reduces the code footprint.

— Debug category. This category defines the Return from Debug Interrupt instruction (rfdi). — SPE vector instructions. New vector instructions are defined that view the 64-bit GPRs as being

composed of a vector of two 32-bit elements (some of the instructions also read or write 16-bit elements). Some scalar instructions are defined for DSP that produce a 64-bit scalar result. — The embedded floating-point categories provide single-precision scalar and vector

floating-point instructions. Scalar floating-point instructions use only the lower 32 bits of the GPRs for single-precision floating-point calculations. Table 1-1 lists embedded floating-point instructions.

— Wait category in the e200z335 only. This category consists of the wait instruction that allows software to cease all synchronous activity and wait for an asynchronous interrupt to occur. — Volatile Context Save/Restore category in the e200z335 only. This category supports the

capability to quickly save and restore volatile register context on entry into an interrupt handler. — e200z3 family implements eight additional (four scalar and four vector) floating-point

instructions.

Table 1-1. Scalar and Vector Embedded Floating-Point Instructions

Instruction

Mnemonic

Syntax Scalar Vector

Convert Floating Point from Signed Fraction efscfsf evfscfsf rD,rB Convert Floating Point from Signed Integer efscfsi evfscfsi rD,rB Convert Floating Point from Unsigned Fraction efscfuf evfscfuf rD,rB Convert Floating Point from Unsigned Integer efscfui evfscfui rD,rB Convert Floating Point to Signed Fraction efsctsf evfsctsf rD,rB

Convert Floating Point to Signed Integer efsctsi evfsctsi rD,rB

Convert Floating Point to Signed Integer with Round Toward Zero efsctsiz evfsctsiz rD,rB Convert Floating Point to Unsigned Fraction efsctuf evfsctuf rD,rB Convert Floating Point to Unsigned Integer efsctui evfsctui rD,rB