LAYER STACKUP ASSIGNMENT

When designing a printed circuit board, a primary consideration is to determine how many routing layers and power planes are required for functionality (within the context of acceptable costs). The number of layers is

determined by functional specification, noise immunity (use of power planes), signal category separations, number of nets (traces) to be routed, impedance control, component density of individual circuits, routing of buses, and the like. Proper use of stripline and microstrip topology is required not only for radio frequency (RF) suppression within the PCB, but also for signal integrity purpose. If signal integrity is ensured, no reflections and ringing will result.

Thus, emissions will subsequently be reduced, too.

It is desirable to suppress RF energy on the PCB rather than to rely on containment by a metal chassis or conductive plastic enclosure. The use of planes (voltage and ground) embedded in the PCB is one of the most important methods of suppressing common-mode RF energy developed internal to the board. The advantage over most other design techniques is that these planes intrinsically contribute to reducing high-frequency power

distribution impedance.

The following stackup assignments are provided only as a guide to determining how to design a multilayer PCB for optimal performance. These assignments are not cast in stone and must be modified as appropriate for

functionality reasons, based on the number of routing layers and power/ground planes required. The important thing to notice is that each and every routing layer is adjacent to a reference (image) plane (power or ground), with the exception of the outer microstrip layer and single-sided designs. The outer microstrip layer must contain only slower speed traces without periodic signals or clocks rich in RF spectral energy. A summary of stackup

assignments is provided in Table 2.1, at the end of this section.

Table 2.1: Example of Stackup Assignments Open table as spreadsheet

Stackup 1 2 3 4 5 6 7 8 9 10

S1 ground power S2

4 layers two routing two planes

ground S1 S2 power

6 layers

S1 power ground S2 ground S3

8 layers

S1 ground S2 ground power S3 ground S4

10 layers six

S1 ground S2 S3 ground power S4 S5 ground S6

For the following stackup examples, observe that where three or more reference planes are provided (e.g., one power and two ground planes), optimal performance of high-speed signal traces may be achieved when routed adjacent to a plane at 0V-reference, not adjacent to the power plane. The reason for this statement is one of the basic fundamental concepts of performing EMI suppression techniques within a PCB.

A plane at 0V-potential is generally screw secured to a metal chassis, thus causing this reference plane to be forced at ground potential. If the reference plane is also at ground potential, this reference plane will be unable to change voltage potential levels, which is one cause of ground bounce and board-induced noise voltage. If the 0V-reference plane is tied hard to ground, common in many designs, only the power plane will modulate at switching frequencies of the assembled PCB; thus, this is one less item to worry about.

Research [4] has shown that known IC sources switch significant current within a PCB, relative to the location of the reference planes within a PCB stackup. Capacitive coupling from IC packages to significant metal structures, including heatsinks and nearby shielding enclosures walls, can lead to significant radiated EMI from switching components. This coupling can be exacerbated or minimized by different choices of layer stackup. A ground plane incorporated as the first layer within a multilayer stackup (Layer 2), instead of the power plane, may provide for enhanced suppression of RF energy owing to reduced parasitic capacitive coupling to the enclosure. This consideration must be remembered when assigning a stackup methodology.

2.5.1 Single-Sided Assembly

The use of single-sided PCBs is generally reserved to products that do not contain periodic signals (clock) or are designed for use in analog instrumentation and control systems. Because of the limited ability to place

components in an optimal manner for short trace lengths, and the need for both a power and ground system, a best case attempt to layout the board must occur.

It is recommended that use of single-sided PCBs be reserved for circuits operating below a few hundred kHz. This low-frequency value is due to various design aspects related to high-frequency circuit requirements, including the applicability of skin effect on traces (traces become highly inductive at high frequencies), the lack of a proper RF return path related to closed-loop circuit requirements, and the need for optimal ground loop control to prevent development of magnetic fields and loop antennas. In addition, single-sided PCBs are highly susceptible to external RF influences such as ESD, fast transient, and radiated/conducted RF susceptibility. The need for

termination and layout techniques for signal integrity is not a primary concern, as the edge transition rate is usually not very fast and the physical dimensions of the PCB usually exceed transmission line lengths. In addition, any I/O interconnects will perform beautifully as a radiating antenna, owing to the lack of a RF return path and the need for flux cancellation.

The easiest approach to the design and layout of a single-sided PCB is to begin by developing the power and ground structure (traces). Next come high-threat signals (clocks), which must be routed adjacent to the ground traces as close as physically possible. After these two steps are completed, the rest of the design can be finalized.

The following requirements are mandatory:

1. Identify all power and ground sources, along with critical signal nets.

2. Partition the layout into functional subsections. Take into consideration requirements of sensitive components and their physical relationship to I/O ports and interconnects.

3. Position all components with critical signal nets adjacent to each other.

4. If different ground nodes are required, determine if they are to be connected together, and if so, where.

5. Route the rest of the board, keeping in mind the need for flux cancellation for traces rich in RF spectral energy, along with the need for ensuring that a RF return path is available at all time.

Figure 2.6 is the worst type of layout for single-sided designs and should "never" be implemented. This is because excessive loop areas are present within the power and ground distribution network. In addition, no provisions exist for a RF return path for critical traces. Note that this figure shows use of dual-in-line components with the same physical dimensions. In real practice, this type of configuration does not exist, as components with different package sizes and the number and type of traces will always be used. The important item to note is the concept behind why this configuration is a very poor layout.

Figure 2.6: Single-sided layout—"very poor design concept."

For single-sided PCBs, only one conceptual design technique provides for suppression of RF energy.

Asymmetrically placed component package sizes, along with unique power requirements, are becoming standard with today's products. With use of these components, Fig. 2.7 becomes applicable during the design cycle. The

routing

S = signal routing layer

layout topology of Fig. 2.7 is commonly found in analog systems—less than 1 kHz—and in nearly all low-speed, low-technology digital products. Note the use of radial routing of the power and ground traces in the figure versus that of Fig. 2.6.

Figure 2.7: Single-layer stackup with radial structure for power routing and flow migration.

Radial routing means that all traces emanate from a single-source location. Signal trace routing becomes easier, as direct-line routing is possible, in addition to ease of connection between radial points. The important item to note is that one must not connect the power and ground traces together on the top part of the PCB in the figure.

The reason for this requirement is easy to visualize. A ground loop would be created, thus defeating use of radial routing, making this layout appear similar to the one that was shown in Fig. 2.6. The only problem with this layout is to determine how to optimally make the connection to the power connector with different radial structures. The PCB designer must be creative in learning how to implement this technique while maintaining the following for optimal performance:

1. Route all power and ground traces in a radial fashion from the power supply. Minimize total routed length of traces.

2. Route all ground and power traces adjacent (parallel) to each other. This minimizes loop currents that may be created by high-frequency switching noise (internal to the components) from corrupting other circuits and control signals. Ideally, these traces should be separated by a distance greater than the width of any

individual trace only when they must be separated for connection to the decoupling capacitor. Signal flow should parallel these return paths.

3. Prevent loop currents by not tying different branches of a tree to another branch.

In Fig. 2.7, the following is to be noted. For a high-frequency application, control the surface impedance (Z) of all signal traces and their return current path. When used in a low-frequency application, instead of attempting to control the impedance of the traces, one must control the topology layout.

2.5.2 Double-Sided Assembly

There are two fundamental layout methodologies for double-sided PCBs. The first is for older technology products (slower speed components) that use Dual-In Line (DIP) packages, located in a straight row or matrix configuration.

Very few products use this topology, and they are usually found only in memory arrays. Figure 2.8 illustrates this type of layout. The second configuration is typical of current design practice.

Figure 2.8: Two-layer PCB with power and ground grid structure.

First Configuration (rarely used) (Fig. 2.8):

For Fig. 2.9, a return trace must be placed as physically close to the high-threat signal trace as possible to permit RF energy to complete its return path back to the source. The power and return trace must also be routed parallel to each other, with decoupling capacitors provided for each and every component that injects switching energy into the power distribution system. With this topology, difficulties in routing may occur. However, significant benefits will be achieved, related to EMC compliance.

ƒ Layer the power and ground in a grid style with the total loop area formed by each grid square not exceeding 1.5 square in. (3.8 square cm).

ƒ Run power and circuit traces at 90-degree angles to each other, power on one layer, ground on the other.

ƒ Place ground traces on one layer—vertical polarization; place power traces on the other layer—horizontal polarization, or vice versa.

ƒ Locate decoupling capacitors between the power and ground traces at all connectors and at each IC.

Figure 2.9: Enhanced double-sided routing to accommodate RF return currents.

When a gridded power and ground layout methodology is used, care must be taken to guarantee that the grids are tied together in as many places as possible. If a grid is not provided, RF loop currents from components will not find a low-impedance return path by any reliable means, thus exacerbating emissions. Routing power and return traces adjacent to each other, using parallel routes, allows for a low-impedance, small-loop area transmission line structure or antenna to exist. With a small-loop area, the RF energy developed will be at such a high frequency that the signals measured may be in the upper MHz range and thus may not pose problems for EMC compliance.

The signal traces referenced to the 0V-return can still create significant current loops, if the distance spacing between the trace and 0V-reference is excessively large.

A problem with double-sided PCBs is how traces are routed between components when a power and ground grid exists. In almost every application, it becomes impractical to fully grid a double-sided board. The most optimal layout technique is to use ground fill to substitute as an alternative return path for loop area control and reduced impedance for RF return currents. This ground fill must be connected to the 0V-reference point in as many locations as possible.

The second layout methodology (Fig. 2.9) for double-sided PCBs is identical to that in Fig. 2.8. The only difference lies in routing of the power and ground traces on both the top and bottom layers. By having two layers available, routing becomes easier to achieve, with loop areas remaining as small as possible.

It is important to note, especially for EMC compliance, that there is no such thing as a double-sided PCB, although they physically exist. For example, when analyzing a double-sided stackup related to EMC compliance, with

standard thickness of 0.062 in. (1.6 mm), the physical distance spacing between the top layer (with components) and bottom layer (with a ground plane or 0V-reference) is often assumed to provide a return path for RF currents present within the top layer. This is illustrated in Fig. 2.10. In reality, the distance spacing between the signal trace and the return plane is physically large compared to the distance spacing between traces. This large physical distance between trace and plane does not allow for optimal flux cancellation. For this example, the field

distribution within the signal trace is approximately one trace width. The physical distance of the field distribution between traces is magnitudes less than the physical distance between trace and reference plane on the opposite side of the PCB. This means that any RF return path that is greater than one trace width distance from the signal source is too far away to perform for optimal return flux cancellation, related to the development of RF energy.

Figure 2.10: Example why two-layer stackups are not efficient for removing RF energy.

The best way to approach a double-sided PCB design is to think of the board as two single-sided designs. Route both the top and bottom layers of the PCB using design rules and techniques appropriate for single-sided designs.

Ground loop control must be maintained at all times, along with a provision for RF return current to exist.

2.5.3 Four-Layer Stackup

There is only one optimal way to perform a four-layer stackup that works well for EMC compliance, although two configurations are possible, each with two options: symmetrical and asymmetrical. Use of reference planes enhances the ability for flux cancellation of RF currents. The physical distance from the signal layer to reference plane is much less than double-sided boards; hence, radiated RF energy is reduced. A four-layer assembly is still not optimal for flux cancellation of RF currents created by circuits and traces. The reason is the same as for

double-sided board—the physical distance spacing between source trace and return path is still excessively large.

Two possible configurations are as follows: