Low-latency Interconnect Optical Network Switch

Low-latency interconnect optical network switch (LIONS) architecture has been pro-

posed in 2013 [27]. It was previously proposed under the name DOS (Datacenter

Optical Switch) in 2010 [83]. The LIONS architecture aims to overcome the limi-

tations of buffer scalability in DOS. The block diagram of DOS/LIONS is shown in Figure 2.16. Switching fabric is based on AWGR which is used in combination with tunable wavelength converters (TWCs). It is possible to route different inputs to a same output simultaneously by using AWGR’s cyclic wavelength routing technique. It also provides fully connected topology and non-blocking characteristics because each output port is connected to each input on distinct wavelength. TWCs are used to tune wavelengths at each input according to the wavelength of the output. Nodes are con- nected with optical channel adapters (OCA) that are used to generate optical packets in conjunction with optical labels. Label switching is used to route packets from inputs to outputs in which labels are sent on different wavelengths[84]. The packet is sent to the label extractor (LE) which extracts label from it by using filter and sends the label to the control plane for routing decision. FDLs are used to store optical payload

2.6. ARCHITECTURES BASED ON AWGRS

temporarily until the routing decision of the control plane arrives. The control plane processes label and sends appropriate wavelength request to TWC to tune on specific

wavelength. TWCs can be configured in nanoseconds scale [27]. The packet is then

sent to the AWGR and is reached to the desired output. It can be seen that each out- put can take N number of inputs on different wavelengths simultaneously. N receivers can be connected with each output, and by using demultiplexing, particular receiver receives packet on specific wavelength after converting it into electrical domain.

LE LE LE TWC TWC TWC Node Rx1 Node Rx2 Node RxN Control Plane AWGR Node TxN Node Tx2 Node Tx1 OCA 1 Rx OCA 2 Rx OCA N Rx OLG PE E/O OCA 1 Tx OLG PE OCA 2 Tx E/O OLG PE OCA N Tx E/O O/E O/E O/E O/E P F C O/E O/E O/E O/E P F C O/E O/E O/E O/E P F C s FDL

OCA: Optical Channel Adapter, OLG: Optical Label Generator LE: Label Extractor, FDL: Fiber Delay Lines

AWGR: Arrayed Waveguide Router, TWC: Tuneable wavelength converter

O/E O/E O/E O/E O/E O/E O/E O/E SDRAM Controller

Figure 2.16. DOS/LIONS Architecture.

Loopback shared buffer is attached with the AWGR which is used to store packets temporarily in case of output port contention or if decision is not made by the control plane within specific FDL delay. In DOS, SDRAM is used to store packets in shared buffer which converts packets to electrical domain. The request is sent to the control plane to reschedule the packet and waits until a grant is received. After receiving the grant, the packet is removed from the shared buffer, it is converted into optical domain and is sent to the AWGR by tuning it into specific wavelength by TWC. LIONS uses three different loopback buffering schemes: 1) Shared loopback buffer (SLB) which was also used in DOS; 2) Distributed loopback buffer (DLB); and 3) Mixed loopback buffer (MLB). DLB uses N separate memory units realizing N queues as compared to single SLB in DOS. It also occupies N input and output ports while MLB occupies only

2.6. ARCHITECTURES BASED ON AWGRS

one output port and is demultiplexed to N ports in loopback buffer. A 40 Gbps(8 × 8)

prototype of the DOS architecture has been demonstrated by Roberto[85].

In both DOS and LIONS, 2-phase arbiter is used in the control plane for packet scheduling. Each input sends request to the arbiter in the control plane and waits for the grant. The number of inputs competing for a given output in the worst case is decreased by a factor k, where k is the number of wavelengths allowed per AWGR output. If k= N then no arbitration is required because there is no contention, but typically k< N, so there is contention, but only the inputs in the corresponding con- tention group need to be examined by the arbiter to grant a request. It is not necessary to look at all the inputs[27].

Scalability of a single stage DOS depends upon the scalability of the AWGR, ca- pacity of shared loopback buffer and the capability of TWCs. Major drawback of loop- back buffer in DOS is its capacity which has been eliminated by using DLB and MLB buffers in LIONS but it still requires costly O-E-O conversion. This loopback buffer is

then eliminated in another version of LIONS named as NACK-LIONS[86] by using all

optical negative acknowledgement technique. In this technique,(N +1)×(N +1) con-

figuration of AWGR is used. Instead of storing packet in loopback buffer, the packet is sent to the N + 1 reflective port which reflects the packet back to the sender by using optical circulator. The dedicated receiver is placed in the sending host which receives the packet coming back to the sender. This packet acts as AO-NACK. The host then resends the packet. NACK-LIONS is also based on the centralized control plane due to which the scalability of this architecture is also limited by the control plane.

Another variation of LIONS with the name TOKEN-LIONS has been proposed in [87]. TOKEN-LIONS uses distributed control plane instead of the centralized con- troller. This distributed control plane does not have global information. TOKEN- LIONS is based on exploiting the saturation effect of reflective semiconductor ampli- fiers (RSOAs). RSOA is deployed at each output port of AWGR and is used as mutual exclusion type of arbiter. Gain saturation effect of RSOA is used to realize mutual exclusion behaviour. Packets are buffered at end hosts instead of input ports. The control requests are sent ahead of the data packets. The request saturates RSOA and

2.6. ARCHITECTURES BASED ON AWGRS

the power is reflected back to the sender which is considered as a grant. After receiving the grant, the packet is sent. On the other hand, if another request comes and previ- ous request is in process, it means RSOA is already saturated and half of the power is reflected back which is considered as a decline at the end host and the request is excluded. The major advantage of the TOKEN-LIONS technique is the scalability of the control plane due to the distributed control plane which does not require global in- formation. However, the delay at input host can negatively effect overall performance due to waiting time of token from RSOAs.

Major advantage in these schemes is low latency because TWCs are fast and pro- vide configuration within nanosecond range. Although, the power consumption and scalability of loopback buffer has been eliminated in LIONS, but the scalability of over- all architecture still depends upon the number of AWGR ports. Hi-LION is another version of LION which is proposed recently to address scalability issue[88]. Hi-LION is a hybrid architecture that employs OPS and electronic packet switching (EPS) us- ing AWGR and electrical switches. This architecture is scalable to hundred thousand nodes. The CAPEX cost of the interconnect is still a major concern because TWCs are expensive devices and are required for each input port of AWGR. Also, multiple receivers per output port is a costly solution in terms of CAPEX cost.