The Lucent AC120 Switch

In this section, we describe the basic architecture of an existing product, the Lucent AC120 switch. The switch was designed to operate at the edge of an ATM network and it is equipped with interfaces for Ethernet, DS-1, DS-3, E1, E2 and OC-3. The switch combines features from both the shared memory switch architecture and the medium shared switch architecture. As shown in figure 6.25, the switch consists of a number of

I/O cards which are attached to two buses. Each bus runs at 600 Mbps. There is also a CPU attached to the bus, which is used for call management. Each I/O card can receive cells from both buses, but it can only transmit on one bus. Half of the I/O cards transmit onto the same bus, and the other half onto the second bus. If one bus develops an error, all the I/O cards switch to the other bus. The buses are slotted and each bus slot carries an ATM cell with an added proprietary header of 3 bytes. Transmission on each bus takes place using the modified time-division multiplexing algorithm described in section 6.4. That is, transmission is done in a round robin fashion among those I/O cards that have a cell to transmit. Each I/O card transmits for one time slot.

DRAM BUS A CPU BUS B . . . I/O ports FIFO FIFO

FIFO FIFO FIFO

Figure 6.26: The architecture of an I/O card

Some of the relevant components of an I/O card are shown in figure 6.26. Each I/O card has I/O devices, a DRAM main memory and a CPU which controls all memory read/write functions, cell queueing, and management of the I/O card. An I/O card can receive cells from both buses, and under normal conditions it transmits only to one bus. It can also receive and transmit cells from its dual input/output ports, which are the actual input/output ports of the switch. The FIFO queues associated with the two buses are used to receive/transmit cells from/to the bus at the rate of 600 Mbps. Therefore, the total rate at which cells may arrive at both input FIFOs (assuming that no cells are being transmitted out) can be as high as 1.2 Gbps.

Cells are transferred from/to the input FIFOs to/from the shared memory using a direct memory access (DMA) scheme. It is possible that an input FIFO may become full. Backpressure is then used to protect against cell loss. This is done by instructing the other I/O cards not to transmit to the card experiencing congestion.

An input and output FIFO also serve all the duplex ports of the I/O card. Cells are written from/to the input FIFO to/from the shared memory at a rate matching the speed of the I/O ports. The switch supports the following interfaces: 1 OC-3, 2 DS-3, 6 DS-1, 4 E1, 6 E2, 5 Ethernet ports. Of the 5 Ethernet ports, four are 10 Mbps ports, and the fifth one can be configured either as 100 Mbps or as a 10 Mbps port.

We now proceed to examine briefly the set of queues maintained in the shared memory, which has a configurable capacity of up to one million cells. There are three queues for all the input ports, and 10 queues per output port, as shown in figure 6.27. An

CBR VBR-1 VBR-2

. . . AQueMan To output port From all input ports

to the bus From buses AQueMan . . . To output port From buses . . .

Figure 6.27: Queueing in the shared memory.

incoming cell from any of the input ports is queued into one of three queues, namely CBR, VBR-1, and VBR-2. These three queues are served to completion on a priority basis, with the CBR queue having the highest priority and the VBR-2 queue having the lowest priority. Traffic coming in from the two buses is queued into one of the 10 queues of the destination output port. Four of these queues are used for CBR traffic, namely, CBR-1, CBR-2, CBR-3, and CBR-4. The next five queues are used for VBR traffic,

namely VBR-1, VBR-2, VBR-3, VBR-4, and VBR-5. Finally, the last queue is used for UBR traffic. A proprietary scheduling algorithm, known as AqueMan, is used to schedule the order in which the cells are transmitted out of these 10 queues. The algorithm utilizes static priorities with additional scheduling rules based on the status of the queues. Specifically, queues CBR-1, CBR-2, CBR-3, CBR-4, and VBR-1 have top priority. That is, they are served to completion before the other five queues can be served. CBR-1 has the highest priority, CBR-2 has the next highest priority, and so on, with VBR-1 having the lowest priority among these five queues. When these five queues are empty, the scheduler will transmit a cell from the remaining five queues, i.e. VBR-2, VBR-3, VBR- 4, VBR-5 and UBR, using an algorithm that takes into account the time a queue was served last (aging factor) and the number of cells in a queue (queue depth factor).

An I/O card is considered congested when the number of cells in its shared memory reaches a high water mark. At this point, entire queues are purged until the number of cells drops below a low water mark.