The silicon microdisks employed in this work were all fabricated from commercially available silicon-on-insulator (SOI) wafers from SOITECR. The wafers consisted of
a 217–344 nm thick silicon device layers (p-type, 1–20 Ω·cm resistivity, 100orienta- tion) on top of a 2–3μm SiO2 buried oxide (BOX) layer. SOITEC wafers were chosen
because of their patented Smartcut process, wherein a thermally oxidized silicon wafer has hydrogen implanted into it at a controllable depth. The wafer is then cleaned and bonded onto another thermally oxidized wafer. The top wafer is then broken on the amorphized silicon layer, annealed to remove defects, and chemo-mechanically
microdisk that has had much of the buried thermal oxide (BOX) removed with hy- drofluoric acid. The characteristic hour-glass shape highlights the region of wafer bonding where the HF etch rate is highest. The silicon device layer thickness is cho- sen so as to provide good confinement for the WGM at the periphery while allowing optical waveguide access through evanescent coupling. The BOX thickness is chosen to minimize radiation into the substrate while still providing good thermal ground- ing of the device. Thermal contact becomes increasingly important for the smaller devices. The associated small pedestal radii greatly constrict the heat flow into the substrate causing power-dependent index of refraction variations. Furthermore, if isolation (see Section 3.5) is necessary, the BOX must be able to be etched through without putting too much stress on the processing equipment. The 100 orientation is ideal for producing high-quality thermal oxides around the devices, encapsulating their sensitive silicon surfaces from the rest of the environment. The resistivity is cho- sen to be>3 Ω·cm in order to minimize the effect of residual free-carrier absorption in the bulk device layer.
3.3
Sample Preparation
In order to aid in the turn-around-time for the fabrication of a working device, a large wafer is subdivided into small sections that are processed individually. Typi- cally, a 150 mm wafer are sent directly to American Precision Dicing for dicing as opposed to individually cleaving shards for samples. Diced samples were preferable over cleaved samples because the resulting roughened but extremely vertical edges provided a higher yield when it came to the transporting of samples between vari- ous processing steps. In addition, the increased uniformity of the samples made it possible to eliminate many size-dependent variations in the processing. Among the various effects, the most problematic size-dependent variability was seen in edge ef- fects during plasma material deposition or plasma dry etching, resist edge beading, and aqueous etchant consumption rates. American Precision Dicing would spin-coat and bake photoresist onto the wafer in a clean hood before dicing the wafer into 1
silica Si disk PECVD cap
Si substrate ebeam resist
Figure 3.2: Schematic illustration showing an SOI microdisk after device layer dry-etching.
cm × 1 cm pieces. The diced wafer would be returned with photoresist intact on a “clam shell” holder, ready for pick and place processing of the individual samples.
After being diced into uniform pieces, the samples were degreased in acetone, isopropyl alcohol, methanol, and DI H2O in order to remove the photoresist and any
other organic material on the samples. If the eventual devices needed to be isolated for taper testing, a 10–50 nm protective cap layer was deposited using plasma-enhanced chemical-vapor-deposition (PECVD). A protective cap was always used if the sample was to be isolated because of the many additional lithography, dry-etching, and wet- etching steps that could damage the thin Si device layer. The cap needed to be thick enough to adhere uniformly to the sample through the entire processing run while being thin enough to have a negligible impact on the etch-induced roughness that occurred during dry-etching. Although SiOx caps were originally used to protect the
Si device layer, SiNx caps were found to be optimal because the initial dry-etching
step could be optimized to etch through both cap and device layer in a single lit plasma step, greatly reducing the complexity of etch optimization. Figure 3.2 shows a schematic illustration of an SOI microdisk after device layer dry-etching through the cap and top silicon. The optimized SiNx cap was deposited using an Oxford
Plasmalab 100 direct dual source RF plasma system. Several samples were affixed to a clean 100 mm Si carrier wafer with a minute amount of thermal paste and surrounded by “dummy” pieces to produce a uniformly thin film across the samples. A gas chemistry of 400 sccm of 5% SiH4/N2, 20 sccm of NH3, and 600 sccm of N2
a 20 second period with a 65% high frequency duty cycle. As each cycle deposited 4.4 nm of material, a ∼ 50 nm thick SiNx cap was deposited with 11 cycles for a
total of 220 seconds. An important note is that the plasma deposition of the cap was experimentally found to damage the top few monolayers of the device layer and was thus avoided whenever possible (see Section 5.6).