DESCRIPTION AND OPERATION
B. Memory CCA (Subtask 23-70-44-870-009-A01)
(1) Address and control signals from the microcontroller arrive at the memory card through J9. The Data bus is 8 bits, the Address bus is 26 bits. Some of the address lines are used to generate control lines. Figure 5 shows a block diagram of the CSMU Memory Board.
(2) Refer to for schematic.
(a) VPP-SWITCH (+12 volts)
1 The VPP-SWITCH line is +12 volt power from the interface and controller card to the memory chips. It is a power supply controlled by the microcontroller to provide a means of isolating the chips during abnormal conditions. The VPP-SWITCH signal is passed to a hold-up bank of capacitors and connected to the VPP inputs of each of the memory chips.
(b) VCC (+5 volts)
1 +5 volts is applied to a hold-up bank of capacitors to become VCC for all of the memory chips.
(c) /MEMO
1 This signal is applied to the gating inputs of the address, data, and control line buffers. When this line is low, VCC is removed from the gating enable lines of: U10 (data side), U15 (both data sides), U19, U35, and U20. Having this line low is a necessary condition for operation.
(d) /MRD, /MWT
1 /MRD is sent to PAL U20 which generates four read control lines: MRD1 through 4.
MRD1 is sent to U10 to control the direction of the data side of the bidirectional buffer. MRD2 and MRD3 are sent to the two halves of bidirectional buffer U15.
MRD4 is sent to U5 to be used as the output enable line for the memory chips (/OE).
2 /MWT is tied to VCC. When pulled low by the microcontroller, the line is sent by U10 as the write enable control line (/WE).
(e) U5 Transceiver
1 Address buffer. This is a dual sided buffer, both sides used to buffer address lines 0 to 15. Gating and direction control lines are all tied to VCC.
(f) U10 Transceiver
1 Dual address and Data buffer. Address lines 16 to 21 are buffered from the upper half of the device as are /OE and /WE. The gating line is tied to ground and the direction line is tied to VCC to fix the direction of this half of the device. The lower half is used as a bidirectional data buffer, buffering data lines MD0 to MD7 to BDA0 to BDA7. This is the A data bus.
(g) U15 Transceiver
1 Bidirectional data buffer, buffering data lines creating the B and C data busses.
(h) U19 Decoder/Demultiplexer
1 This is a four to sixteen multiplexer creating chip enable lines CE(0.15). The multiplexer is selected by MA26 going low.
(i) U35 Multiplexer
1 This is a three to eight multiplexer creating chip enable lines CE(16.23). The multiplexer is selected by MA26 going high and MA25 going low.
(j) U20 Programmed PAL
1 This is a programmed array logic device which creates chip selects and memory read control lines for the data buffers. It creates chip enable lines CE(24.28) when MA25 and MA26 are high.
(k) Flash EPROM
1 Each of the 27 flash EPROM memory chips are 1 megabyte devices. They are arrayed on three data busses.
Table 4. EPROM Memory Chips
Bus A Bus B Bus C
U3 U1 U12
U4 U2 U16
U8 U6 U17
U9 U7 U18
U13 U11 U30
U21 U23 U31 (not installed)
U22 U24 U32
U25 U27 U33
U26 U28 U34
U29
(l) U14 EEPROM
1 The nonvolatile memory is an electrically erasable programmable read only memory used for storing BIT and memory pointers.
Figure 5. (Sheet 1 of 1) CSMU Memory Board Block Diagram (GRAPHIC 23-70-44-99B-808-A01) C. Controller CCA A1 (Subtask 23-70-44-870-010-A01)
NOTE: Figure 2001 provides the schematic for PN 722-4052-001, 133 for PN 722-4052-002, 134 for PN 722- 4052-003 and on, and 132 for PN 722-4159-001 and on. In the following
A1 description, reference designators in parenthesis are applicable to PN 722-4159-00X, Figure 2002. Those not in parenthesis are applicable to PN 722-4052-00X.
(1) Audio Input Processing
(a) The SSCVR has four audio input channels, three narrow band voice channels (CH 1, 2, 3) and a wide band cockpit area microphone channel. In the 30 minute version, each channel and the area microphone feeds data to separate solid state memory. The three narrow band channels are mixed together in the 2-hour version to be stored in separate memory for redundancy. The area microphone has extended memory to 2 hours as well.
Individual narrow band channel memory stays at 30 minutes.
(b) As shown in Figure 6, the input channels feed analog signals to a CODEC device which provides an 8-bit mu-law serial digital signal to the ADPCM. An 8-bit mu-law signal is a logarithmic conversion of the analog signal which simulates the dynamic range of a 13-bit linear signal. The ADPCM compresses the eight bit signal from 8 bits to 3 bits each sample. The ADPCM is divided into two sections, an encoder and a decoder.
It can provide full duplex encode and decode at 8 kHz or half duplex single encode or decode at 16 kHz.
1 Input Channel 1
a Audio Channel 1 is transformer coupled to a frequency shaper through transformer T2 (T2). After the transformation, a copy of the signal is sent through R10 (R122) to the mixed channel input. For Channel 1 only, the FSK-TIME input overlays the voice input. The frequency shaper consists of R6, R7, R8, C7, C8 and C9 (R143, R142, R144, C137, C136 and C117).
b This network brings the frequency response up to a 3.5 KHz bandwidth.
Diodes D2 (D2) and D3 (D1) provide overvoltage protection for the CODEC input, U7(U1)-17, 18. The output of the CODEC, U7(U1)-13, provides the 8-bit mu-law signal to the ADPCM, U8(U13)-12. The output of the ADPCM, U8(U13)-15, is sent to the data packer, U9(U21), as well as used as a feedback for the operation of the ADPCM. The output signal is combined with the other two narrow band channels as signal DAT-IN-NAR to the data packer.
Figure 7 shows a block diagram of the ADPCM.
2 Input Channel 2
a Audio Channel 2 is transformer coupled to a frequency shaper through transformer T4 (T4). After the transformation, a copy of the signal is sent through R55 (R140) to the mixed channel input. The frequency shaper consists of R11, R12, R37, C10, C11 and C38 (R138, R137, R139, C153, C152, and C133).
b This network brings the frequency response up to a 3.5 KHz bandwidth.
Diodes D4 (D12) and D5 (D11) provide overvoltage protection for the CODEC input, U10(U2)-17, 18. The output of the CODEC, U10(U2)-13, provides the 8-bit mu-law signal to the ADPCM, U11(U14)-12. The output of the ADPCM, U11(U14)-15, is sent to the data packer, U9 (U21), as well as used as a feedback for the operation of the ADPCM. The output signal is combined with the other two narrow band channels as signal DAT-IN-NAR to the data packer.
3 Input Channel 3
a Audio Channel 3 is transformer coupled to a frequency shaper through transformer T3 (T1). After the transformation, a copy of the signal is sent
through R50 (R118) to the mixed channel input. The frequency shaper consists of R38, R39, R40, C39, C40 and C41 (R120, R121, R136, C114, C113, and C131).
b This network brings the frequency response up to a 3.5 KHz bandwidth.
Diodes D6 (D4) and D7 (D3) provide overvoltage protection for the CODEC input, U12(U3)-17, 18. The output of the CODEC, U12(U3)-13, provides the 8-bit mu-law signal to the ADPCM, U13(U15)-12. The output of the ADPCM, U13(U15)-15, is sent to the data packer U9 (U21), as well as used as a feedback for the operation of the ADPCM. The output signal is combined with the other two narrow band channels as signal DAT-IN-NAR to the data packer.
4 Input Channel 4
a Audio Channel 4 is transformer coupled to the CODEC through transformer T1 (T3). Diodes D10 (D9) and D11 (D10) provide overvoltage protection for the CODEC input, U17(U10)-17, 18. The output of the CODEC, U17(U10)-13 provides the 8-bit mu-law signal to the encode ADPCM, U21(U12)-12. The output of the ADPCM, U21(12)-15, is sent to the data packer, U9 (U21) as well as used as a feedback for the operation of the decide ADPCM. The output signal is DAT-IN-AREA to the data packer.
5 Mixed Channel
a The mixed channel is coupled to a frequency shaper. The frequency shaper consists of R44, R45, R46, C42, C43, and C44 (R200, R201, R190, C199, C198, and C183). This network brings the frequency response up to a 3.5 KHz bandwidth. Diodes D8 (D18) and D9 (D19) provide overvoltage protection for the CODEC input, U15(U19)-17, 18. The output of the CODEC, U15(U19)-13, provides the 8-bit mu-law signal to the ADPCM, U16(U20)-12. The output of the ADPCM, U16(U20)-15, is sent to the data packer, U9 (U21), as well as used as a feedback for the operation of the ADPCM. The output signal is DAT-IN-MIX to the data packer.
Figure 6. (Sheet 1 of 1) Audio Input Processing (GRAPHIC 23-70-44-99B-809-A01)
Figure 7. (Sheet 1 of 1) ADPCM (GRAPHIC 23-70-44-99B-810-A01) (2) Audio Output Processing
(a) The 3 bit values going to the data packer are also looped back into the decompression section of the ADPCM transcoder, one for each channel. The wide band channel uses one transcoder for encoding and another for decoding. Each narrow band channel uses one transcoder for both encoding and decoding. The decoded 8 bit mu-law samples are converted back to analog signals by the DAC sections of each CODEC.
These analog signals are mixed and routed to the audio monitor output. The signals are also present at the audio test point connector. Figure 8 provides an Audio Output Processing block diagram.
(b) All four feedback signals: MONITOR1, MONITOR2, MONITOR3, MONITOR4, are combined to the input of U3A (U23A). Also added is the TONE signal from the processor which passes through a low pass filter. The output of U3A (U23A) passes to buffer U3C (U23C) and becomes AUDIO-MON-H to the phone jacks. Figure 9 provides a Real Time Audio and Playback Audio block diagram.
Figure 8. (Sheet 1 of 1) Audio Output Processing Block Diagram (GRAPHIC 23-70-44-99B-811-A01)
Figure 9. (Sheet 1 of 1) Real Time Audio and Playback Audio Block Diagram (GRAPHIC 23-70-44-99B-812-A01)
(3) FSK Input Processing
(a) The FSK input enters the SSCVR through any of the three transformer coupled voice channel inputs as shown in block diagram, Figure 10. The voice inputs are mixed by an operational amplifier in the mixed audio channel. This operational amplifier is built into a
CODEC that is part of the mixed channel. The FSK signal is in the form of a 2.45 Vrms sine wave burst of 32 cells of 1.302 milliseconds each. Each cell time is encoded with a frequency of 3607 Hz for a logic 0 or 4163 to 4223 Hz for a logic 1.
(b) The operational amplifier output is buffered and scaled by 0.5 by operational amplifier U23C (U18C). The buffered signal is AC coupled to Phase Locked Loop, demodulator U25 (U4). The demodulator has a center frequency of 3.9 KHz and generates two digital output signals, FSK-IN and FSK-LOCK. These signals are processed by the data packer.
FSK-IN is a logical inverse of the demodulated data. FSK-LOCK is active low. A low logic level indicates a detection of the presence of a FSK input burst. A state machine in the data packer uses the FSK-LOCK and FSK-IN signals to synchronize with the FSK time cells. The data packer converts the serial signal to parallel format.
(4) Digital Interfaces
(a) The digital interfaces are protected from transients by combinations of resistors and diodes. The ARINC 429 input and output interfaces are implemented with a custom IC U24 (U24). The OMS TX output is buffered by two operational amplifiers, U23A (U18A), U23B (U18B), in a differential driver configuration. Table 5 lists the signal, type and number of lines.
Table 5. Digital Interfaces
Signal Type Lines CPU Interface
GMT RX ARINC 429 2 input Data bus
CMU RX ARINC 429 2 input Data bus
OMS TX ARINC 429 2 output Data bus
OMS RX ARINC 429 2 input Data bus
GBE TX RS 422 2 output Serial port
GBE RX RS 422 2 input Serial port
GBE CTS RS 422 2 input Serial port
GBE RTS RS 422 2 output Serial port
MAINT Discrete 1 output I/O port output pin
GBE PRES Discrete 1 input I/O port input pin
(b) The GBE inputs are converted from RS 422 to single ended digital by receiver U28 (U29).
The receiver outputs go directly to the controller CPU serial port inputs. The GBE outputs are driven from the controller CPU serial port pins through driver U29 (U38).
(c) The MAINT output is connected to relay K1 (K1). Normally the relay is in the open condition, causing MAINT to float. When a signal is received at the positive terminal of U26D (U17D), Q4 (Q100) is closed causing the relay to energize. This causes the contacts to close, causing MAINT to go low.
(d) For PN 722-4052-004 and on (post service bulletin 980-6020-XXX-23-03) and PN 722-4159-001 and on, a FET Q5 (Q4) and a gating resistor R133 (R247) are added. The FET is turned off when power is not applied, and appears as an open circuit (fault) at the maintenance discrete output. When power is applied, the FET is turned on and appears as a short circuit to reflect whatever condition the maintenance discrete relay indicates.
(e) GBE PRESENT input is connected through an RC filter, R121 (R46), C101 (C220) to an input port on the CPU, U14(U26)-22. The input port pin has a hold up resistor, R120 (R230), to +5 volts. On the aircraft, this input would be strapped to ground.
Figure 10. (Sheet 1 of 1) FSK Processing Block Diagram (GRAPHIC 23-70-44-99B-813-A01) (5) Rotor Speed Processing
(a) Figure 11 provides a rotor speed processing block diagram. The input signal is limited by a resistor-diode network which clamps the voltage to 2.1 volts peak. The signal represents a rotor frequency of 7 to 77 Hz. This signal is coupled through transformer T5 (T5) to comparator U30C (U39C). The comparator is biased to 2.6 volts on the positive input and 2.5 volts on the negative input. The biases provide hysteresis to avoid jittering.
The comparator converts the rotor speed input to logic level pulses of the same frequency.
Figure 11. (Sheet 1 of 1) Rotor Speed Processing Block Diagram (GRAPHIC 23-70-44-99B-814-A01) (6) Microphone Monitor Interface
(a) The Audio Monitor output from the SSCVR feeds the headphone jack on the microphone monitor. The ERASE and PUSH-TO-TEST signals are generated from pushbuttons in the microphone monitor. Both signals are conditioned by comparators, U30A (U39B)
and U30B (U39A), which drive the CPU input port pins. Both are transient protected by diode and resistor networks. The ERASE signal has a pulldown resistor, R94 (R241), at the comparator input. The PUSH-TO-TEST input has a pullup resistor, R109 (R245), to +5 volts.
(b) The STATUS signal is generated through U26C (U17C) to turn on FET Q3 (Q3). This pulls down the STATUS-L line. This will allow the 0.8 milliampere current from U23D (U18D) (STATUS-H) to pass through the meter to STATUS-L. Refer to Table 6 for the connection, type, and description of the microphone monitor interfaces.
Table 6. Microphone Monitor Interface
Connection Type Description
Channel 4+ Analog SSCVR audio input from area microphone
Channel 4+ Analog Audio return from Channel 4+
Monitor Analog SSCVR audio output signal
Monitor return Ground SSCVR analog ground
+18 volts Power Power monitor from SSCVR power supply
+18 volt return Ground Power return for +18 volts Erase Digital discrete Active high input to CPU Push-to-test Digital discrete Active low input to CPU
Status + Analog 0.8 ampere current source from SSCVR
Status FET switch Active pulldown to ground
(7) System Controller (a) Processor
1 The CPU, U14 (U26), is an Intel 80C196K microprocessor with a clock frequency of 20 MHz. It uses an 8 bit data bus with 32 Kilobytes of ultra violet EPROM, U20 (U35 or U36), and 8 Kilobytes of static RAM, U19 (U33). The CPU has a multiplexed address/data bus and uses and address latch, U1 (U34). Chip selects and ready state generation logic are implemented in the memory interface FPGA (U27). The MI drives a CPM interface bus of 27 address bits. The lower address lines, 0 to 15, are driven directly from the CPU bus, and buffered by the MI. The upper memory address lines, 15 to 26, are driven by registers in the MI. Refer to Figure 12 for the system controller block diagram.
(b) Memory Chip Power
1 The +12 volts (VPP) power to the CPM is controlled by a CPU output port which drives a combination of two comparators; U26A (U17B), U26B (U17A); and two MOSFET switches, Q1 (Q1), Q2 (Q2).
2 To write to the chips, the 12V-SWITCH line from the CPU is high. The output of U26A (U17B) is then low. This turns Q2 (Q1) on, applying VPP to VPP-SWITCH to the chips. U26B (U17A) is off, output high, holding Q1 (Q2) off.
3 On Reset, to prevent spurious writing to the memory, the +12 volt power is removed.
Signal 12V-SWITCH is low, U26A (U17B) output is high. This turns Q2 (Q1) off.
U26B (U17A) is on, applying a low to Q1 (Q2), turning Q1 (Q2) on. VPP-SWITCH is thus held to ground level.
(c) Audio Input
1 The controller reads audio data from the data packer through three FIFO buffers, U2 (U31), U5 (U32), U6 (U30), for the mixed, area, and narrow band data respectively.
(d) RESET (/RST) for PN 722-4159 CCA
NOTE: The reset circuit is included on the PN 722-4159 CCA. For PN 722-4052 CCA the reset circuit is included in the A2A2 power supply capacitor board.
1 The reset output, /RST, is high when the system is up and running. When the +5 volt supply drops below limits (approximately 4.75 volts), /RST goes low. This is the signal to the microprocessor that power integrity has been lost. The system is reset here. The PDI causes the power down mode. The reset circuit monitors +5 volts through device U25A. U25A is a comparator which compares +5 volts (divided to 2.5 volts) against a 2.5-volt reference.
2 The reference voltage is supplied by VR2 through R225 to U25A-2. The +5 volt signal is divided through R223, R226, R222 to provide voltage to U25A-3. When the +5 volt supply drops to 4.75 volts (approximately), the output of U25A-1 switches low. C218 is a filter capacitor to prevent noise from tripping the circuit. C217 provides input filtration. R224 is a 1-megohm resistor providing positive feedback for hysteresis. When U25A-1 is low, U25B-7 is high, turning off Q101. When Q101 is off, the reset signal is pulled low by being pulled down through R214.
3 When power resumes, R221 and C50 form a delay in the 5-volt signal of about 100 milliseconds (RC time constant of 47 milliseconds). This makes sure that the +5 volt supply is up and stable before releasing the reset signal on the microprocessor.
The U25B comparator has hysteresis feedback through R206 to prevent circuit toggling at the threshold trip point. The 2.5-volt reference is applied through R209 to U25B-5. C212 is used for power supply decoupling of U25. U25B is an open collector device, therefore R210 acts as a pullup resistor. The 3.3-volt Zener, VR3, prevents U25 from toggling Q101 when the +5 volt supply is not fully powered.
Current limiting is provided by R211.
Figure 12. (Sheet 1 of 1) System Controller Block Diagram (GRAPHIC 23-70-44-99B-815-A01)
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