Memory Devices

In microprocessor systems, the data are stored in special devices called mem-ory. There are two main types of memory devices: read-only memory (ROM), which permanently stores in the microprocessor operating program, and

Input

Control

Control

Sample Hold

Analog input Hold output

C_H A₂ S₁

A₁

+ +

– – Output

FIGURE 2.33

Sample-and-hold circuit.

1mV 2 V 2 V 2 mV

100 nS 200 nS

Output

Output Input

Input

FIGURE 2.34

Actual oscilloscope records of signals at input and output of sample-and-hold circuit.

random access memory (RAM), which is designed for temporary storage of intermediate calculations. As the permanent storage device is designed only for reading the preset program, it is ROM. Opposed to this is RAM, which is designed for continuous data exchange with external devices (i.e., for high-speed reading and recording of new data at any random moment upon an external device query). There are many subtypes of these two major memory devices. For example, some types of ROM can be reprogrammed as required during operation. For example, you can erase the old relay protection settings and input the new ones. These types of ROM are called erasable programmable read-only memory (EPROM). The S/H circuit should be connected to the ADC input in series with an anti-aliasing filter (see Figure 2.35).

EPROM was invented (U.S. patent 3,660,189, 1972) by Dov Frohman, the founder and former general manager of Intel Israel who is widely respected as a leader and innovator in the worldwide technology and semiconductor industry (see Figure 2.37). EPROM remained Intel’s most profitable prod-uct well into the 1980s. At first, you could erase the contents of the EPROM only by using ultraviolet radiation sent through a special window in the chip body within 10–15 minutes. There were special devices designed for this purpose. Later, the electrical erasable programmable read-only memory (EEPROM or E²PROM) allowed erasing and rewriting the contents of the memory with electric signals sent to special inputs. This has turned out to be very convenient for reprogrammable microcontrollers and microprocessor-based protective devices (MPDs). However the disadvantage was that con-ventional EPROM had a far higher capacity and longer life than even very large EEPROM.

In recent years, a new type of permanent memory, so-called flash memory, has become available. Unlike EEPROM, which provides bit erasing and bit over-writing of data, flash memory erases and writes data by large blocks. Since the erasing of memory takes a good deal of time, such large-block operations sig-nificantly accelerated the process compared to that of old EEPROM devices.

Flash memory was first introduced by Fujio Masuoka, DSc, of the Toshiba Corporation in 1984 (see Figure 2.38). The flash memory is based on metal-oxide semiconductor field effect transistors (MOSFETs). These transistors are equipped with insulated control electrodes, called gates, and are controlled through supplied electric potential.

Thanks to very effective sealing, the electrical charge (defining the transis-tor state) is stransis-tored in the MOSFETs for a very long time. In order to change

Anti-aliasing

filter Sample-and-hold (S/H) circuit

converterA/D

FIGURE 2.35

DPR analogue signal input circuit.

the state of the transistor (i.e., to erase the memory of the cell formed by such transistor), you only have to discharge its control junction, that is, remove the electric charge. Memories based on this principle can store data for years and allow up to 50,000–100,000 rewrites. It is quite clear that the integrity of memory based on the electric charge depends on the memory cell’s self-discharge rate, which is highly affected by various adverse factors such as ionizing and radiation, among others.

All types of permanent memory are nonvolatile, that is, those in which the information is not initialized upon power-off. In fact, the part of the relay protection program defining the MPD algorithm (i.e., determining the type of defense: differential, distance, current, etc.) should not be modified under any circumstances while the other part of the program can be changed by the customer (e.g., the part responsible for operation settings and protection mode). In order to separate these two parts, sometimes they are designed as two separate chips, one of which stores rewritable data (EEPROM), and

Input1

8-input multiplexor type ADG1208 (Analog Devices, Inc.).

the other stores nonrewritable data (the so-called software key [SWK] based on ROM). In order to modify DPR operation, it is required to replace the SWK chip with the new one. For automatic control of ROM and EEPROM serviceability, the recorded memory array is summed and encoded as a cer-tain number, which is referred to as the checksum, recorded in a specially reserved cell. In test mode (usually at microprocessor loading), it scans the contents of the memory and compares it with the checksum. If a discrepancy is detected, further work is blocked by the microprocessor. In some advanced systems, there are two EEPROM devices running in parallel. If one of them finds such a discrepancy (i.e., memory damage), the memory is automatically

FIGURE 2.37

Dov Frohman, inventor of the EPROM.

FIGURE 2.38

Fujio Masuoka, DSc, inventor of flash memory (Toshiba Corp.).

overwritten from the second intact EEPROM. Also, there are several types of RAM, such as static RAM (SRAM) and dynamic RAM (DRAM).

A standard cell of a static binary memory is a binary transistor-based trigger consisting of two cross-connected (ringed) inverters (logical NOT elements) and switching transistors providing access to the cell (see Figure 2.39).

Such a design is bistable, that is, when switching from one state to another, it retains its position until receipt of a modifying electric impulse. Thus, the memory based on this principle (see Figure 2.40) does not require periodic reloading for saving data, but it remains volatile and entire data are lost upon power-off.

Sometimes, an external lithium battery is installed on the motherboard and used to keep the data safe upon power failure. Typically, such cells last many years, but when the voltage is reduced they must be replaced. However, if you simply remove this cell, all the data recorded in such memory will be

Reset

Standard static RAM (SRAM) cell based on six CMOS transistors.

V_CC

Volatile static RAM (SRAM) type AS7C256 (32k × 8 bit) based on CMOS transistors (Alliance Semiconductor).

lost. Therefore, such a battery should be replaced when the external power supply is connected in parallel to the battery holder.

There is also a special kind of memory called nonvolatile SRAM (nvSRAM).

This memory can store data after disconnection of external power thanks to a built-in tiny lithium battery (see Figure 2.41). This memory is faster than EPROM and EEPROM, so sometimes nvSRAM is used as a permanent rewritable memory (i.e., another form of EEPROM). Standard SRAM can be used if we need a relatively simple low-capacity memory with low power consumption. For example, it is used for registers and cache memory.

Large operating memory in devices is realized as DRAM. Each cell of the memory contains a low-capacity capacitor C and a solid-state switch VT, installed in a single chip (see Figure 2.40). The capacitors are charged upon inputs of single bits into the cell or discharged upon input of zero bits into the cell. The solid-state switch “locks” the cell and retains the charge inside the capacitor. To access a particular cell, you select its address in rows and columns (see Figure 2.42).

In practice, the capacitor and solid-state switch functions in DRAM chips are performed by CMOS microtransistors that, like capacitors, are capable of accumulating and storing the charge within a certain period of time thanks to the efficient internal sealing. Advantages of this design include relatively low cost and large capacity of memory. However, because the capacitance generated by microtransistors is very small, the stored charge diffuses rap-idly and the data must be updated within regular intervals to avoid data loss (actually, this is why this type of memory is called dynamic). This process is called memory regeneration (memory refresh) and is implemented by a spe-cial controller.

The entire string of “cells” in DRAM is rewritten within a certain period of time called the regeneration step, and in 8–64 milliseconds all rows in the memory are updated. Such memory regeneration process significantly “slows

V_CC

The design and appearance of nonvolatile SRAM.

down” the system, because during this process the exchange of data with the memory is impossible.

Therefore, the regeneration based on the conventional row search is not applied in modern DRAM units. There are several more cost-effective ver-sions of the process, including supplementary operating assemblies installed inside the DRAM chip. It is clear that the actual design of the DRAM unit (see Figure 2.43) is much more sophisticated than its simplified schematic circuit diagram.

In recent years, a variety of advanced DRAM types (EDRAM, FPM DRAM, EDO DRAM, SDRAM, DRRAM, etc.) have been developed. Mere enumera-tion of them can take a lot of space, and consideraenumera-tion of them is far beyond the scope of this chapter.

To sum up, I’d like to emphasize only one very important feature of the DRAM: its high sensitivity to electrical noise and to radiation. Electrical interference caused by internal circuits, or penetrating from the outside, can lead to spontaneous switching of dynamic memory cells, containing a single bit, into the opposite value. Initially, it was assumed that the effects of radiation were caused by alpha particles emitted from plastics insulating a memory chip, pollutants contained in the chip itself, and packaging materi-als under the influence.

As mentioned above, recent progress in the field of nanotechnology has led to a significant reduction in the size of semiconductor elements (reaching microns and even fractions of a micron), a reduction of thickness of semi-conducting and insulating layers, a reduction of operating voltage, and an increase in operating speed and the number of elementary logic cells in one

Row Address Selection

Column Address Selection

Data a0

a1

a₂ a₃

VT C

FIGURE 2.42

DRAM schematic circuit diagram.

A0 A1 A2 A3 A4 A5 A6 A7

Address register Row add. buffer Row decoder

Auto/self refresh counter

Memory Array

S/A & I/O gating Col. decoder Col. add. buffer

Col. add. counter

Read DQM control Write DQM

control DQM

DQi Data out

Data in

Burst counter Mode register set

CLK/CLK CKE /CS /RAS /CAS /WE DQM Timing register

DQM

A8 A9 A10 A11 BA0 BA1

(a)

(b) FIGURE 2.43

(a) Realistic design of 64 Mb synchronous DRAM: electrical flowchart. (b) Realistic design of DRAM: the appearance of certain DRAM module types, which are widely used in PCs.

device. All this has resulted in a sharp rise of the memory cells’ sensitivity to ionizing radiation. This sensitivity is so high that ordinary (that is, com-pletely normal) background radiation at sea level is dangerous for the mem-ory cells. High-energy particle currents coming from the space are especially dangerous. Even one such particle penetrating the memory cell generates secondary streams of electrons and ions, causing spontaneous switching of a simple transistor or capacity discharge at charge memory elements. The problem is compounded by the ever-growing use of memory elements in modern microprocessor structures. A great many modern highly integrated circuits constituting microprocessor devices contain large embedded mem-ory elements with completely uncontrolled operability.

The problem of the sharp increase in sensitivity to ionizing radiation is relevant not only to the memory elements, but also to high-speed logic gates, comparators, and so on, that is, practically for the whole of modern microelectronics. The worst thing is that the random microprocessor failures caused by electromagnetic noise and radiation may be temporary, such as spontaneous changes in the contents of memory (RAM) and registers, while internal damages may not be overt. Both of these types of failures cannot be detected by any tests, and can show up at the most unexpected moments.

2.5.3 Microprocessors

The microprocessor is the central DPR assembly controlling the operation of all other assemblies and performing arithmetic and logical data operations.

The modern microprocessor is practically a complete control system. It has a sophisticated internal architecture and represents a very large integrated circuit built on silicon base layers. It is manufactured by special technology involving chemicals, gases, and radiation.

The processor contains a number of microtransistors interconnected with ultrathin aluminum connecting channels enabling interaction for recording and processing of data, and providing the performance of numerous func-tions. The first model of the 4004 microprocessor, announced by Intel in 1971 (see Figure 2.44), contained “only” 2300 transistors and performed about 60,000 computations per second. The 486 series processor, widely used today in DPRs, contains 1.6 million transistors, while the Pentium IV processor has 42 million transistors and performs hundreds of millions of operations per second.

Today, microprocessors are the most complex element among electronic devices. Hundreds of manufacturing steps with surpassingly strict require-ments to the purity and accuracy of each are required to produce modern microprocessors. Initially, the first very thin layer of silicon dioxide is grown on the base under a high temperature. Then the base is covered with photo-graphic emulsion that is disintegrated by ultraviolet radiation, which is then covered with the so-called template (a template with the circuit pattern).

During the photolithography process, ultraviolet radiation, passing through the template, forms the circuit pattern on the base. Light-exposed

areas of photolayers become soluble and are washed out with a special sol-vent during the further processing, thus exposing the corresponding part of the silicon dioxide layer not protected by the template. Chemicals etch out the unprotected areas of silicon dioxide, revealing the silicon dioxide pat-tern on the base. In order to separate the finished layer from the new one, an additional thin silicon dioxide layer has to be grown on the circuit pattern.

Then it has to be covered with a microcrystalline silicon layer and another photolayer. Subsequently, the second layer has to be grown in the same way.

A special template is used for the exposure of each microprocessor layer.

The formation of semiconductors with desired conductivity and p-n transi-tions of the transistors from the pure silicon is performed during the all-ion-implant process, where the areas of the silicon base exposed to ultraviolet light are bombarded with ions of different impurities. The ions penetrate into the base, providing the necessary electrical conductivity of these areas.

Coating and etching have to be repeated several times. After this, very small gaps in the layers are left for the interlayer compounds. These gaps are filled with metal atoms joining the layers of the future microprocessor (in today’s microprocessors, the number of layers may reach 20 or more.

The ultrafine layers of metal are left at the edges of the chip for attaching the external microprocessor pins. The total manufacturing cycle consists of more than 250 stages, after which the microprocessor has to pass thorough testing and then be integrated into the protective enclosure.

The microprocessor performs the following functions:

Reading and decoding commands contained in the main memory

•

Reading data from the main memory and registers of external

•

device adapters

Data processing and entry into the main memory and registers

•

Generating control signals for DPR output devices

•

FIGURE 2.44

Inventors of the world’s first microprocessor.

Microprocessor software determines the specific tasks performed by the microprocessor. Microprocessor types differ by memory type and size, set of instructions, processing speed, the number of input and output lines, and data capacity. In general, a microprocessor flow diagram can be as that depicted in Figure 2.45.

The CPU is the binding assembly of any microprocessor device, its core.

Some of the superior modern microprocessors have several cores working in parallel under the control of a master core (see Figure 2.46). They are called

Data address

generators Program

sequencer ^Programmemory Data memory Memory

Program memory address

Program memory data Data memory data

Arithmetic units ALU RAC Shifter

Core

Serial ports Timer Host

interface port

External data bus External address bus Flags

0 1

Data memory address DAG 1 DAG 2

FIGURE 2.45

An example of the internal structure of a commercial microprocessor with integrated memory and some supplementary elements.

Master core Slave

Core 1

Slave Core 2

Slave Core 3

FIGURE 2.46

Structure of multicore processor. Master core: control (lead) core; and slave core: (executive) leaded core.

multicore processors. The core of a conventional CPU includes an arithme-tic logic unit (ALU), a register-accumulator (RAC), a multibit shifter, data address generators and program sequencers, and an internal bus.

The arithmetic logic unit performs arithmetic or logical operations on the data presented in binary or binary-coded decimal code. The result is stored in the so-called register-accumulator.

RAM cells represent the RAC, but, unlike the main memory, they use shorter commands for data exchange (i.e., the RAC is the fastest memory device of the microprocessor).

The multibit shifter with a set of multiplexors provides processing of shift logical instructions and multiplication and division operations. In a binary computing unit, a one-position shift to the left of the binary number has the same effect as multiplying by 2 (see Figure 2.47), and a right shift has the same effect as dividing by 2 (zero is shifted to a new position). Since the shift-ing speed significantly exceeds the speed of multiplication and division operations, it is widely used as a tool for program optimization.

Data address generators and program sequencers coordinate the interaction between different parts of the microprocessor. The device includes the clock speed generator, clock-pulse driver, and program sequencer. The framing bit is generated by a crystal-controlled oscillator equipped with an external crystal oscillator. The frequency of the clock speed generator determines the speed of the microprocessor.

The program sequencer (or controller-sequencer) provides for temporarily halt-ing the execution of one program in order to promptly fulfill the other pro-gram that is currently more important. Propro-gram sequencer services interrupt procedures, receive interrupt requests from external devices, determine the priority of the request, and send the interrupt signal to the microprocessor.

Microprocessor memory is designed for short-term storing, recording, and transmitting data used in the calculations directly to the next operating

Doubling with shifter. 10111: a binary image of 23; and 101110: a binary image of 46.

ticks. Microprocessor memory is based on registers and provides high-speed DPR operation, as the main memory is not always capable of providing the required speed of recording, searching, and data reading.

The microprocessor interface system is designed for communication with other DPR devices. It includes the following:

Internal interface of the microprocessor

•

Buffer storage registers

•

I/O control circuit and system bus (the I/O port is interface equipment

•

providing connection of the other device to the microprocessor) In order to extend and improve microprocessor functionality, both stan-dard peripherals and additional circuit boards with chips can be connected to the microprocessor and system bus. These include the math coprocessor, I/O coprocessor, and interrupt controller, among others.

The math coprocessor accelerates operations with binary floating-point num-bers, binary-coded decimal numnum-bers, and trigonometric functions. The math coprocessor is controlled by the main microprocessor. It has its own instruc-tion system and operates in parallel with the latter. The result includes the acceleration of operations in dozens of times over. Typical modern micropro-cessors are, as a matter of course, equipped with math copromicropro-cessors.

The I/O coprocessor works parallel with the microprocessor. It significantly accelerates the execution of I/O procedures when servicing multiple external devices, and deallocates the microprocessor from I/O procedures, including direct memory access mode.

The system bus provides communication between various elements of the

The system bus provides communication between various elements of the

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