Memory Mapping

In order to help us understand the role of the address bus and the concept of memory mapping, we take another look at the memory chips themselves. Figure 1schematically shows a hypothetical memory chip, which has storage for 16 words (each 8 bits in length) of information.

Actual memory chips typically store many hundreds of kilobytes and have a correspondingly larger number of memory access pins. You should observe however, that in our hypothetical chip of Figure 1.1

Fig. 1.1- Schematic of a Hypothetical 16-Word Memory Chip

The memory chip is composed of two functional sections - the Boolean decoding logic section and the actual storage section. The decoding section is responsible for controlling the transfer of data to/from the computer data bus from/to a storage address in the chip. This access control is based upon the status of the memory address pins (MA3..MA0), the Read/Write pin and the Chip Enable (or Chip Select) pin.

The Chip Enable (or Chip Select) pin is the access device for the chip. In order to use the chip, the Chip Enable pin must be set either high or low (depending on the manufacturer's design).

The Read/Write pin is used on RAM chips to define whether data should flow into or out of the chip. Depending upon the high or low state of this pin, data will be written to or read from the appropriate address location in the chip. As an example, if the microprocessor in our hypothetical system is to force the memory chip to place its fourth row (0011) of storage (ie: 00000111) onto the data bus, then it would have to set:

MA3 = 0 MA2 = 0 MA1 = 1 MA0 = 1 Read/Write = 1 Chip Enable = 1

thus accessing the third row in the memory chip.

The microprocessor controls the memory chip address pins and chip enable (select) pin, by setting appropriate lines on the address bus high or low. In other words, a selection of address lines from the microprocessor is connected to pins on the memory chips. These lines are selectively set or reset by the microprocessor in order to make the memory chips respond in the desired manner. The Read/Write line of the memory chip is tied to a corresponding driver line on the microprocessor.

The dilemma that immediately arises is that if there are many identical memory chips, connected to the address bus of a microprocessor system in an identical manner, then all the chips will respond simultaneously to each request from the microprocessor. This is clearly ridiculous, since it would imply that no matter how many memory chips we have, we would only effectively have the storage capacity of one chip. Since it would be equally ridiculous to have scores of specially designed memory chips, the problem is overcome through the use of "memory mapping"

techniques. Each memory chip in a microprocessor system must have a unique connection to the microprocessor address bus, otherwise a conflict occurs. This unique addressing is achieved through address bus decoding logic, as shown in Figure 6.6. In a simple system, this logic can be implemented through Boolean logic gates.

Let us now assume that two of the memory chips in the system shown in Figure 1.2, both have a structure identical to the hypothetical one shown in Figure 1.2. The following Boolean logic could be used to decode the address lines for chip 1:

MA0 = A0 MA1 = A1 MA2 = A2 MA3 = A3 Chip Enable = X1 where:

Memory chip number 2 in the system could have the following Boolean logic gates for address bus decoding:

MA0 = A0 MA1 = A1 MA2 = A2 MA3 = A3 Chip Enable = A4 . X2

where:

This arrangement implies that memory chip 1 can only be accessed (enabled) when all microprocessor address lines A4 through to A15 are low. Otherwise chip 1 remains locked.

Memory chip 2 can only be accessed when address line A4 is high and lines A5 to A15 are low.

Otherwise chip 2 remains locked. Table 1 shows the effect that this has from the microprocessor's point of view. A number of such chips could be selectively "mapped" so that to the microprocessor, all address locations from 0000 0000 0000 0000 to 1111 1111 1111 1111 can be accessed, with no two chips responding to the same address.

Table 1 - Memory Mapping of Identical Memory Chips in Figure 6.6 to Unique Locations with respect to Microprocessor

Memory mapping is a vitally important concept in computing because most devices are interfaced to the microprocessor via a range of memory addresses. For example, the parallel to serial conversion chip (UART) in a computer system has a number of internal registers. One of the registers in the chip contains data that tells the device how to perform its function and another register is used for incoming data and yet another for outgoing data. All these registers are mapped, just as if they were normal system memory. The microprocessor communicates with them as though they are normal memory locations, when in reality they are often part of another special purpose chip or system.

The same memory mapping technique can be used to interface disk-drive controllers and graphics controller cards to a microprocessor within a computer system. A range of memory locations or registers in these devices are mapped into system memory as if they are normal memory chips. The microprocessor moves data to and from them as though they are normal memory locations. The devices that are mapped onto the system use the data supplied by the microprocessor to do their respective tasks. For example, the graphics controller card uses the data provided by the microprocessor to create an image on a screen. This is shown in Figure 2.

Fig.1.2 - Using Memory Mapping Techniques to Create a Common Shared Area of Memory (or Registers) to Transfer Data To and From Non-Memory Devices (eg: Graphics Controller Card)

Most computer systems are composed of many memory chips and each and every memory chip must ultimately have a unique address. Most computer users would be familiar with the concept of memory in the form of a card that plugs into the address/data bus structure of the computer.

Each card may hold a number of memory chips. The manufacturers of the card generate the decoding logic that enables the entire card to be treated as one large "chip" (because each of the memory chips is actually decoded on the card itself). Users then complete the memory mapping function by setting dip-switches on the card to make the entire card map into an appropriate region of the computer's system memory. The dip-switches enable one card to be easily mapped into a number of different memory locations so that they can be used on a range of computers.

Newer computer systems resolve the problem of memory mapping for cards by using very sophisticated address and data bus structures. Each device that plugs into the address and data bus structure has to be equipped with a special interface that is capable of responding to commands issued by the CPU. The memory mapping and configuration process can then occur automatically. Although this may appear, to end users, to be a very useful solution to the memory mapping problem, it creates considerable problems and costs for those that have to generate cards for such systems.