Our market research data suggested that the on board memory should be either 2 5 6 kilobytes (KB) or 1 megabyte (MB) . The amount depends on whether 6 4 K DRAMs or 2 5 6K DRAMs are used . At the time the design was started, 2 5 6 K parts were i n short supply. Therefore, using 64 K D RAMs was a strategy to cou nter that s hortage .
The function of the memory controller is to carry out 4 00-ns read and write operations and to refresh its RAM chips. This control ler con-
ON-BOARD CONTROL 022-BUS CONTROL
a: 0 <f) rJ) UJ () >- o w < a; U CI: a. < CI: o "- < a: CI: w o w >-- >- <( ::;: � (9 MEMORY SEQUENCER AUXILIARY DEVICE CONTROLLER
I
SLAVE MACHINEI
ARBITRATION MEMORYI
MACHINE ARBITER I MASTER I MACHINE II
I
<f) a: w N z 0 a: I u z >- rJ)Fig ure 4 Block Diagram of the Control A rchitecture
BUS
INTERFACE GATE ARRAY
Digital Tecbnicaljournal 4 1
the Micro VA X II CPU Board
tains a Q 2 2-bus scatter-gather map that handles transfers between the Q2 2 -bus virtual memory and on-board physical memory.
Memory access is controlled by the memory arbiter. This arbi ter checks for outstanding memory access requests i n a fixed-priority sequence at the ends of 200-ns idle cycles and 4 0 0 -ns memory cycl es . It also c h ecks for requests from the Q22 -bus slave machine , the memory-refresh counter, and the CPU chip, in that order. The fixed-priority sequence resolves col l ision requests for memory usage . If the arbi ter requires exclusive control of the memory subsystem, a locking mechanism built into the subsystem prevents contention.
When the CPU chip requ ires a memory-read lock, the memory arbiter will stall the chip and direct the Q 2 2 -bus arbitration machine to sus pend other bus activity. Those actions will hap pen only after any pending memory cycles of the slave machine have been completed. The arbitration machine will retai n Q 2 2 -bus master ship until the writejunlock cycle of the CPU c h i p frees t h e b u s . Unti l t h e arbi tra t i o n machine becomes Q22 -bus master and while the CPU chip i s stalled, the memory arbiter will perform the demand-driven refresh cycles and resolve slave-deadlock cycles from the Q 2 2 -
bus . As each memory cycle is completed, the
memory arbiter c hecks t hese requests again, and either the Q 2 2-bus or the refresh-memory cycle can begin at the next clock edge . If no Q22-bus or refresh requests are pending, the arbiter anticipates that a CPU-chip cycle will be next.
That anticipation and the fix e d -priori ty sequence save a lot of program execution time . The CPU chip makes about seventy percent of all memory references. Slave machine accesses by the 1/0 bus devices occur twenty percent of the time (a maximum burst rate , not the aver age rate) , and those by the refresh counter, two perce n t . (The remainder are i d l e cycles . ) Therefore the controller, b y anticipating that the CPU chip-rather than the I/0 bus or the memory-refresh counter-wi ll make the next memory access, allows a memory cycle of 4 0 0 ns, instead o f 6 0 0 ns. (The 600-ns cycle would be necessary because the address strobe of the CPU chip wou ld have to assert before the mem· ory cyc l e c o u l d start , t h u s was t i ng o n e microcycle .)
When timing microcycles, the memory arbi ter enables the memory sequencer at phases
4 2
coincident with the CPU chip's entry to a new microcycle . This enabl ing happens even though the sequencer does not yet know whether or not there will actually be a memory access by the CPU chip. Not until three phases later can the sequencer determine whether or not the address strobe has been asserted for a memory reference . If so, the sequencer enables the con tinuation of the anticipated memory access . After that cycle completes, the next memory access wi ll be enabl ed , and the procedure
repeated. If not, the sequencer " k i l l s " the
cycle and runs another poll loop after checking for Q 2 2 -bus slave or refresh requests. Not antic ipating a memory access would reduce per for m a n c e by a p p r o x i m a t e l y t h i rty - t h re e percent.
The memory sequencer generates the row and column address strobes, sets up reads and writes on each byte , and handles pariry genera tion and detection . The auxiliary device con troller can "stretch " the memory cycle of the C PU chip to synchronize its timing with slower devices, such as the TOY clock and the boot ROM .
The scatter-gather map converts between the 22 -bit virtual addresses of the Q 2 2 -bus ( 4 MB addressable) and the 2 4 -bit physical addresses
of the memory (up tO 1 6MB addressable) . As
defined by VAX memory management, the 4MB
is divided into 8 1 9 2 pages of 5 1 2 bytes eac h . The 2 2 -bit virtual address consists of a 1 3 -bit page number and a 9-bit offset to the addressed byte in that page . The 24 -bit physical address consists of a 1 5 -bit page number and a 9-bit offset. An entry in the map for each 5 1 2 -byte page and offset points to a location in physical memory. Each physical address has four byte masks that select which bytes are inactive on any memory reference.
There are, of course, other ways tO map addresses ber�'l'een the 1/0 bus and memory. One way is one-ro-one address trans lation, which in this case would have restricted physi cal memory to 4 MB . Another way is first tO map one-ro-one into the lowest 4 M B of memory. Then, the CPU chip can perform the transla tions and data transfers to the proper pages in the address space of the remaining memory. Unfortunately, this approach is unacceptable
due to its effect on performance. A third way is
to have fewer than 8 1 9 2 mapped pages. In this case , programmers might have tO provide the ir own mapping software for many real-time IjO
Digital Technical journal
app l i cat ions . That typ i c a l l y i nvo lves D MA access to large numbers of RAM locations . None of these methods proved as satisfactory as the use of the scatter-gather map.