Much like the two-transistor half-bridge, the FCML topology is built from pairs of com-plementary transistors. In the schematic of Fig. 2.11, S4A and S4B represent two of these complementary pairs. Also like the half bridge, parasitic inductances in the commutation loop arising from PCB layout similarly hinder performance; during fast transitions, energy stored in this inductance can lead to overshoot in vDS to the detriment of EMI or device ratings, while slowing or damping the commutation (typically done by increasing the gate re-sistance) would lead to additional turn-on loss (as noted in Section 2.2.1). The GaN switches in this work enable designs that are simultaneously low loss and low weight due to their high-speed switching capability. However, leveraging these devices in FCML converters requires mitigation of the parasitic inductance [117]. Converter designs using a lateral layout (i.e. all switching devices are on a single PCB side) do so by employing local bypass capacitors that effectively short the commutation energy through a low inductance path [70, 118]. Lateral layout converters are easier to assemble and debug, with most components confined to a single side.
However, a vertical design – where complementary components are mirrored on opposite sides of the PCB [67, 73, 80], as illustrated in Fig. 2.12 – can improve thermal management and high-voltage capability. For instance, dual-sided cooling is straightforward, while the high-voltage standoff capability of the PCB substrate helps address clearance requirements.
While local bypass capacitors are precluded in this configuration, the use of internal copper layers and via stitching can effectively null much of the inductance arising from the
com-1.6mm Prepreg Thickness = 0.1 mm
Flying Capacitors GaN Devices
S
4AS
4BFigure 2.12: Cross section showing commutation loop between a given pair of complementary switches. Internal layers and vias create an electrically-thin vertical layout on a single PCB; the cross-sectional area inside the PCB (shaded red), and thus the corresponding loop inductance, can be greatly reduced with this approach.
mutation loop passing through the converter PCB. This “electrically-thin” approach [119]
reduced the loop inductance of [73] from 8 nH to 2.7 nH. However, as that design used
“switching cell” daughter boards soldered to the main PCB, both blind and buried vias were necessary to create the electrically-thin routing without overlapping mounting pads.
This work uses a vertical layout but eliminates daughter boards, and instead places the switching cells on the main converter PCB. A custom 6-layer stackup and buried vias are then used to create the electrically-thin path within this PCB. This custom stackup requires the thickness of the prepreg between the outer copper and first inner layers to be as thin as possible, as illustrated in Fig. 2.12. The general intuition is that all current paths should be routed to tightly couple (i.e., to be in close proximity) with their corresponding anti-parallel return paths. Eliminating the daughter boards does remove an element of modularity, but improves manufacturability, power density (less substrate material), and reduces loop inductance by decreasing path lengths.
2.4.1 Parameter Extraction using Finite-Element Analysis
To analyze the benefits of the above approach, finite-element analysis was conducted in Ansys Q3D. Trace and pad shapes were imported into Autodesk Inventor, where three-dimensional geometries with thicknesses corresponding to copper and laminate specifications in the stackup were defined. While Ansys does have a toolchain to import PCB files directly, many vias were used to stitch the inner layers, and their inclusion would have created a complex body to process. Instead, via stitching was simplified by forming a solid copper mass where the vias connect layers. Previous work noted that this does not decrease accuracy significantly; the resulting discrepancy is on the order of the precision at which the physical system can be experimentally measured [62].
The model of the switching cell is shown in Fig. 2.13. To reduce the computational do-main, only a subset of the volume around a single switching cell is within the simulation geometry. Additionally, extraneous copper from adjacent gate drive circuits is omitted for simplicity. While there is likely some coupling into these traces, inclusion in this analysis
Shorted Capacitor Pads Top Switch (Open)
Bottom Switch (Short)
Top Copper Layer
Inner Copper Layers
Figure 2.13: 3D model of a switching cell with buried vias, as imported and meshed in Q3D.
would likely only be of interest for EMI purposes and have little effect on the commutation loop concerns of this section. Additionally, the multilayer ceramic capacitors are treated as ac short circuits (though the pads for capacitors on adjacent cells are shown for illustrative purposes). While the physical real will have a more nuanced interaction with the magnetic fields present in the commutation loop, the short circuits allow the analysis to be approxi-mately limited to trace geometries and routing for the purposes of evaluating switching cell design. However, the lumped models of the ceramic capacitors may be added in series with the relevant segments of the computed model for a more practical number. Finally, to ensure the current loop is correctly closed, the bottom transistor is replaced with an ideal short cir-cuit while the top switch is left open, as indicated in Fig. 2.13. This way, a source and sink stimulus can be established on the respective left and right edges of the two, adjacent top copper layers in the boxed region. The red and blue arrows are used to indicate the general flow of commutation current from the source to the sink of the electrical net, matching the convention in Fig. 2.12.
This analysis was solved at a frequency of 100 MHz, which is the order of magnitude matching the frequency of oscillation between device capacitances and commonly observed loop inductances. The primary loop inductance from the drain of the top switch, through the PCB and to the source of the top switch, was calculated to be 0.939 nH. For the two sets of two series, four parallel ceramic capacitors serving as flying capacitance for most of the switching cells, the lumped component inductance amounted to an additional 0.65 nH [120].
Thus, an overall inductance of 1.59 nH was expected for this design, representing a further substantial decrease in parasitics for the state-of-the-art.
2.4.2 Simulation of Commutation Loops in SPICE
The inductance reported above represents a lumped quantity; However, the finite-element analysis also generates a full impedance matrix for any number of ports defined in the model.
LTS
Figure 2.14: Spice model of commutation loop implemented as a component in LTSpice using parameters extracted from Q3D finite-element analysis.
Additionally, ac resistances associated with each current branch are also calculated, and use-ful for informing the damped behavior at high frequencies. This is valuable when simulating the effects of the commutation loop, as using the lumped inductance alone produces an un-derdamped response when the only circuit resistances are the nominal on-resistance of the transistors and the ESR of the capacitors. Additionally, it may be useful to examine the inductance between adjacent switching cells, especially when operating under high module output current. Therefore, a multiport equivalent model was also extracted.
Though not always ideal for simulating switching circuits, Spice is the appropriate plat-form for nodal analysis involving these parasitics. In Fig. 2.14, the equivalent model for half of a switching cell (one flying capacitor) is represented in LTSpice schematic format. The values in the .param declaration are mostly computed and transferred from Q3D directly, specifically the inductance and the coupling terms (with prefix K). Here, rather than defining the unit cell to contain the two complementary devices and the adjacent flying capacitors, as illustrated in Fig. 2.11, only the path through a single flying capacitor is modeled. Choosing this configuration as the building block allows the model to be easily repeated between each switch pair for the whole converter. On the contrary, choosing the unit cell as illustrated in Fig. 2.11 would only correctly capture the dynamics of every other switching cell. Fur-thermore, both intuition and the results of finite-element analysis indicate stronger coupling between copper traces on a single side of the devices (in parallel planes) versus those on the opposite side (also parallel, but with significant offset). As such, the coupling terms corresponding to the latter are safely omitted in this model.
Finally, it is important to note that the ac resistances calculated in the finite-element
Lpar
(a) Test setup for measuring overshoot. A coaxial connection mitigates high-frequency pickup.
(b) Results for the proposed commutation loop, showing greatly reduced drain-source overshoot.
Figure 2.15: Experimental characterization of drain-source voltage overshoot during commutation as a means of comparing loop parasitics between designs.
element model are dependent on frequency, whereas resistances modeled in spice are not. To emulate this effect, a series-parallel transformation was used to add this damping resistance in parallel with the partial inductances to provide the desired resistances at high frequency.
The step-response of the system is thus is damped as expected, but without the use of excessive series resistances.