The challenges outlined above have motivated an exploration of diverse converter technolo-gies and topolotechnolo-gies. While this section is not meant to provide an exhaustive list, it does highlight many inverter implementations that have achieved significant performance against the targets, or otherwise have desirable attributes. In general, these systems have been enabled by wide-bandgap devices [39], and 2- and 3-level designs are ubiquitous – mostly improving in step with devices and packaging technology [40].
1.2.1 Two-Level Half-Bridge
The traditional half-bridge, or six switch module in a three-phase converter, is is the 2-level system common to extant electric vehicle drivetrains. This topology is illustrated in Fig. 1.2b, where the ac output node can toggle between the positive and negative rail of the dc bus (i.e., the levels of the 2-level waveform). While silicon insulated-gate bipolar transistors (IGBTs) have been the workhorses of such converters at both high-voltage and high-current for some time, these devices are accompanied with high switching losses and thus limit the switching frequency. As such, significant filtering of the output of each line phase would be required to drive an HSP machines described above.
However, silicon carbide devices – which allow for very high blocking voltages with com-mensurate conduction losses and significantly lower switching loss as silicon IGBTs – have expanded the operating range for these converters [41]. Additionally, very high output cur-rents (and therefore torque) can be achieved when the devices are paralleled [42]. This is evident in the Tesla Model 3 powertrain [34], the first commercial electric vehicle to use silicon carbide. However, other than paralleling novel devices, there is little room for inno-vation on this straightforward, but limited topology. Additionally while these devices have reduced intrinsic, dynamic parasitics (e.g., gate charge and output capacitance), switching transition speeds and frequencies are still typically limited to under 100 kHz. While the lower parasitics do reduce switching energy, the fact that the devices must charge and discharge
Vdc
(b) Six-switch, three-phase converter. (c) A representative 2-level waveform over one fundamental period. The switched node, vac, alternates between Vdc and 0 V.
Figure 1.2: The common, 2-level bridge topology, with corresponding single-phase output waveform.
to the entire bus voltage each commutation is the dominant factor, as switching loss scales with the square of this voltage. This large rate of change in voltage, dv/dt, also means a significant amount of effort must be spent on output filter design if it is meant to interface with any HSP machines requiring sinusoidal input current. As such, much of the literature is spent optimizing magnetics and switching parameters to find the frontier of this space [43].
A significant amount of effort has also been spent minimizing dc bus inductance to allow for faster switching. This parasitic inductance on the dc side of the switches stores energy while the device is in the on state. When the device switches off, this energy charges the switch drain-source capacitance. If the parasitic inductance is large enough, at high currents this stored energy can cause detrimental overshoot of the device. Unless this inductance can be reduced, the only other recourse is to slow the speed of the device transition, though this would incur greater overlap loss (see Chapter 2). As such, the best designs use in-depth modeling, careful routing and innovative manufacturing methods to achieve a low-inductance, simulated (though not measured) to be as low as 6 nH for 1 kV designs [44].
1.2.2 Three-Level T-Type
The 3-level T-Type converter phase-leg is illustrated in Fig. 1.3a. Here, the dc bus is divided into three levels, +Vdc/2 and −Vdc/2 as well as a neutral midpoint. The four switches in each phase leg (12 switches total in a three-phase converter) connect the ac output to these levels in a sequence defined by the specific modulation strategy to generate the waveform shown Fig. 1.3c. Note, a four-quadrant switch is needed at the midpoint connection to prevent self-commutation (through the diodes) to the wrong state when inductively loaded. For example, a positive current flowing out of the vacnode would always turn on D3 before D4 without the
Vdc
(c) A representative 3-level, PWM wave-form over one fundamental period. The switched node, vac, alternates between +Vdc and 0 V or −Vdc and 0 V depend-ing on the point in the line cycle.
Figure 1.3: The 3-level topologies highlighted in this chapter, with corresponding output waveform.
reverse switch S2 to selectively prohibit this path as needed when driving positive current at the negative half of the line cycle. Since the four-quadrant switch only sees half of the dc bus voltage, lower voltage devices may be used – but the other two devices will need to block the full dc bus voltage. Additionally, complementary switch pairs S1/S3 and S2/S4 only commutate during half of the cycle, so implementations with silicon IGBTs can still yield improved performance [45].
Of course, switching losses can be significantly reduced by using silicon carbide, as seen in a recent 250 kW scale demonstration [46]. This system used commercially available devices to achieve 98.5% efficiency and 25 kW/L with liquid cooling. To leverage the reduced costs and improved current handling of IGBTs, [47] further proposed paralleling a silicon IGBT with a silicon carbide MOSFET to make a hybrid switch for S1 and S4 to reduce conduction losses; the silicon carbide MOSFET would be used for fast turn-on and turn-off, while the IGBT would be switched during the rest of the on-time to carry the majority of the current and reduce conduction losses. To ensure correct current sharing between the two device types, busbar design and module arrangement was again a significant design consideration.
Inductance in the dc link was as high as 12 nH, though the differences between paralleled switches was on the order of 2 nH [48].
1.2.3 Three-Level Active Neutral-Point-Clamped
The active neutral-point-clamped (ANPC) is the second promising three-level design, shown in Fig. 1.3b. The dc bus is again divided into three levels, with six switches in each phase leg. The switching scheme for generating the three level waveform ensures that each device only sees half of the bus voltage, allowing the use of lower voltage devices and operation at reduced switching loss [49]. Additionally, complementary switches groups (S1+S3)/S2 and (S2+S4)/S3 only commutate during half of the cycle, while the switch pair S5/S6 only commutates once per line cycle. This effectively means S5 and S6 can be devices with better conduction characteristics at the cost of worse dynamic parasitics. Indeed, in the megawatt-scale demonstration for NASA, General Electric used proprietary 1700 V, 500 A silicon carbide half-bridge modules for both S1/S2 and S3/S4 half-bridges and a single 1700 V, 600 A silicon IGBT half-bridge for S5/S6 [50]. Depending on the commutation loop (i.e., the loop between silicon carbide or silicon devices), the reported inductance ranged from 6.5 nH to 17.5 nH for this 2.6 kV design [51]. As it were, this high bus voltage meant that even divided among three-levels, the output still experienced extremely high dv/dt. As such, a major caveat remains given that significant amount of the total inverter mass was from to the ac output filter alone (a factor of three greater than the contribution from the power modules).
Nonetheless, it a remarkable milestone for this system to have delivered 99% peak effi-ciency at 12 kVA/kg – as demonstrated at a full megawatt. While this system might not be scalable, in that the power modules, filtering considerations and thermal management were purpose built for a single power level, it highlights the benefit of a new architecture and new semiconductors for the application. Indeed, to process that much power a specially designed
“pump-back” system was also engineered to circulate current between two prototypes of the three-phase converter [52]. This test setup can thus serve as a useful reference when the array of Chapter 4 is tested at higher power levels in future work.
1.2.4 Higher-Level Topologies
Multi-level versions of the T-Type and ANPC converters can be found in the literature, but require significantly more switches and series-stacked dc capacitors as the number of levels increases. Additionally, routing of the commutation loops becomes much messier, as many more midpoint connections and half-bridge nodes need to overlap and intersect. Thus, the overhead from routing these networks becomes impractical for this power-dense application.
The cascaded H-bridge and [53] and modular multilevel converter [54] are other (typically) higher level-count topologies that have been applied to high fundamental frequency drives.
However, in both topologies, the capacitors must be sized to support the full fundamental current. This imposes a significant constraint on the size of the capacitors used in each application: for large output currents, these capacitors must also be large – on the order of hundreds of microfarads to millifarads, making them necessarily bulky. The exact analysis of this power density implication is explored further in [55]. Additionally, in the modular multilevel converter, the phase-legs must manage current between the upper and lower halves of each phase-leg to guarantee the appropriate output and minimize circulating currents that do not deliver power to the load. Both topologies have been able to show good harmonic performance and exhibit cell-level redundancy (see Chapter 5), but in the end, fail to deliver on power density.