Full 2D ML detector

To get rid of the use of ZF, which limits the amount of noise that can be handled, because of its noise amplification, we also implemented full 2D ML detector.

We implemented the Full 2D ML detector by first using PR equaliser along track, to shape the signal to a selected target. The response across track for two or three track interference is assumed to be the target across track and therefore needs no equalisation. Viterbi detec- tors are then used for the ML detection, both along and across track. One of the ML detectors is a 2D multi-bits Soft Output Viterbi Algo-

rithm (SOVA) detector, used to first eliminate the effect of either ISI or ITI. A regular 1D (Soft or Hard Output) Viterbi Algorithm (VA) detector is then used in the other dimension, to detect the signal out of the interference left.

Joint-Track ML Along Track

In the first implementation, 2D SOVA is used along track as a joint track detector, to detect the signal by removing the ISI. The likelihood (BMs) of receiving all possible adjacent bits across tracks is saved from the state with the best SM (shortest distance) in the history, for use in the next VA detector. There are four BMs per symbol for a two-track interference and eight BMs per symbol for a three-track interference.

Following this procedure means, memory enough to save 4 or 8 float- ing numbers for all bits of each track is needed, which will be used in the next VA algorithm.

The saved BMs of adjacent symbols from adjacent tracks are then used as the DMs of a VA that is carried out across the tracks. BMs and SMs are then determined and trace-back conducted after processing all tracks of given bit positions. The final detected bits (in hard decision VA) or likelihood of bits (in soft decision VA) are determined from this process.

Multi-Bits ML Across Track

In the second implementation, 2D SOVA is used across track as a multi-bit detector. It is used to detect the signal by removing the ITI. The likelihood (BMs) of receiving all possible successive interfered bits along track, is saved from the state with the best SM (shortest distance) in the history, for use in the next VA detector. In this case, memory enough to save 8 floating numbers (for 3-bit target along track) for all tracks is needed. This means less memory will be needed since we have

only 8 tracks in our implementation.

The saved BMs, for symbols of the same track, are then used as the DMs of a VA that is carried out along the tracks. BMs and SMs are determined and trace-back conducted after processing each symbol. The final detected bits (in hard decision VA) or likelihood of bits (in soft decision VA) are determined from this process.

Example of 2D SOVA Implementation

The 2D SOVA, described above, is a novel procedure designed to facili- tate the full concatenation of a 2D SOVA to another ML detector. This arrangement makes it possible to reduce the complexity of using full 2D detection on multiple tracks. Rather than using a single 2D detector to detect 8 tracks as presented in works like [68], it uses two ML detectors, one along and the other across track, to carry out the detection process.

If a single detector is to be used for joint detection of 8 tracks with a target of length 3 along track, a detector of complexity in the order of 28∗3 = (16, 777, 216) is needed. But if the method presented here is used, with three-track interference, then the complexity will be of the order 8 ∗ 23∗3 = (1, 024) for the 8 tracks. Example of the 2D SOVA procedure is explained below, and illustrated in figure 3.8.

The example in figure 3.8 assumes a target of [0.4, 0.8, 0.8, 0.4] along track. It also assumes two track interference, where the contri- bution from both tracks is the same (IT I = [1, 1]).

As usual, the histories and SMs must be initialised at the beginning of the process, according to the knowledge of starting points of the data. The example assumes a detection depth (trace-back length) of four symbols. These are seen as the 4 columns of the history in each of the Present and Next state. The leftmost column (in green) in the

Figure 3.8: Example of 2D SOVA. State Metric=Red in each state. Green column in state with minimum state metric is the output.

present state is the oldest set of BMs, while the rightmost column is the newest. Figure 3.8 captures portion of the process at an arbitrary time when the received signal is assumed to be -4.13, and the history as shown in the figure.

The SM of each state is the minimum BM from the latest (right- most) set of BMs. They are shown in red, in the Present state histories. To determine the output of the detector at this instance, the minimum among those SMs is determined. Assuming SMs of all the states not shown are higher than the ones shown, we can see the SM of the third state is the minimum. Therefore, the earliest column of BMs in green, from the third state, will be taken as the output. These 4 BMs rep- resent the likelihood of 00, 10, 01, and 11. The two bit represent bits

from two adjacent tracks interfered together.

Euclidean distance, of the received signal from the reference dibit responses of the branches, is determined as shown in the squared brack- ets on the branches. These are the DMs of the branches. Each DM is added to the SM of the state from which it comes from to get the BMs. The four BMs terminating in each state are now saved as the newest columns of the history for the Next state. The minimum of those new BMs in each state is the new SM for the state. History from the state where the new SM is derived is cut and appended to the history of the Next state (except the earliest history in green). These Next state metrics are now used in the next cycle, for the next received symbol, as the Present state metrics. The procedure continues until the end of the track or band of symbols is reached.

The four outputs of the 2D SOVA will now be used as DMs of a Viterbi detector applied across track. Across track means, the first symbol of the first track, the first symbol of second track, the first symbol of third track, and so on, are considered to be successive sym- bols. The same thing is done with second symbols of first, second and all other tracks. This continues until the end of the data is reached.

A similar arrangement can be implemented with 2D SOVA first ap- plied across track then VA along track. The difference in procedure will be that there will be no need of finding output in each cycle. The final output across tracks can be found after all the symbols across tracks are processed.

As explained before, regular normalisation is needed to prevent over- flow of registers. Register exchange is shown here because it is concep- tually simpler. But trace-back method is preferred for hardware im- plementation, to reduce need of multiplexers for moving histories from

one state to another.

3.4 Forward Error Correction

Forward Error Correction (FEC) is used in communication and mem- ory channels to reduce the errors found in data by identifying and possibly correcting the errors obtained in the channel. In binary data, parity bits are the building blocks of FEC algorithms.