2 Fundamental Module Blocks
2.9 Module Hardware Block 8: The Processing Power
The processing power of every module is dependent upon the type of microcon-troller and its ability to execute millions of instructions per second (MIPS).
Semiconductor manufacturers like Panasonic, ROHM, NXP, Renesas, Freescale, Maxim Semiconductor, ST Microelectronics, Infi neon, Siemens, Fujitsu, Texas Instruments, Microchip, NXP, Toshiba, Atmel, Silicon Labs and many more have already developed line of processors primarily meant for the AEC Q100 qualifi ed automotive applications. Renesas and Freescale Semiconductor (formerly Motorola) have captured the biggest market share of automotive microcontrollers.
In Fig. 2.1 , the processing block is drawn separately from the memories, but in real world, a major share of microcontrollers keeps the program storage of code and critical data inside the microcontroller (RAM, EEPROM and Flash EEPROM). The types of microcontrollers used in the industry are optimally packaged for hardware and software features. There is a trend of integrating more and more functionality be packaged inside the silicon chips. More functionality with less pin count means added software commands to confi gure the ports properly before the intended fea-ture is to work in a typical microcontroller. Majority of microcontrollers share com-mon pins to allow multiple functions.
Computing architectures like Von Neumann, Harvard or modifi ed-Harvard with pipelining, multi-stage pipelining or no-pipelining have been used in automotive computing.
As a brief note to the current trend in the industry, some of the salient functions and features of a typical automotive computing architectures and resources are listed below:
• Von-Neumann Architecture, Freescale STAR12, Fig. 2.3
• Von-Neumann Architecture, Renesas R32C Family, Fig. 2.4
• Modifi ed-Harvard Architecture, Microchip PIC18F Fig. 2.5
In terms of computational speed, a mission critical control computer like elec-tronic engine controllers must be fast enough to compute: Proper operational func-tions; process background self-tests for the system integrity—and must maintain active communication link with vehicle modules connected to system interfaces like sensors and actuators. The core operation of engine controller is to calculate best
2 Fundamental Module Blocks
fuel-to-air mixture ratio, and an intelligent ignition-fi ring-algorithm for the optimal engine performance under varying vehicle power, and load-demands—at all times—in all weather conditions. The secondary operational features of engine computing node are to monitor, and control the battery charging by controlling the alternator magnetic fi eld strength—with added energy management tasks. Last, but not the least it maintains a proper handshake with safety and security electronics mechanism to permit or prohibit an engine start sequence.
It has been recognized that engine controllers require higher computational needs compared to any other real-time application installed in a typical vehicle.
However, this excludes the multi-media components not discussed so far.
D EEPROM=4K
84
Another good example to recognize the signifi cance of computational power is the functions of an airbag module—a safety-critical computer, which requires an extremely fast processing speed to execute an inevitable algorithm to safely, and rapidly deploy the airbag (s). Such a fast demand of program-instructions execu-tions is needed during the event of an imminent vehicle crash, where an airbag computational node is forced to do extensive decision-making algorithm within a short duration of time in order to deploy the airbag (s). The event begins when the vehicle crash-sensor gets triggered; and from that point onwards a short-window of time is available, where the module processing node has to execute the most sophis-ticated algorithm of ‘its life time’ to take the airbag deployment decision—in an attempt to save an occupant’s life.
Another semiconductor company named Microchip has developed line of micro-controllers suited for automotive applications that uses Harvard architecture offer-ing Reduced Instruction Set Computer (RISC). A similar set of resources are available like the one Renesas and Freescale microcontrollers offers, but offered with Harvard architecture where data-memory, and instructions-memory are sepa-rately accessed. In some cases multi-stage pipeline computing is also offered.
However multi-stage pipeline computing in real-time applications require thorough review of architecture to meet the worst case deterministic tasks scheduling risks, and risks mitigation due to inherent perils of pipeline hazards like stalls, and data- dependencies. Smart compilers can take care of many issues, but not always; all use-cases could be tested and comprehended in real-time dynamic challenges of distributed vehicle processing.
It is important to understand the distinction of two similar names by learning their simple attribute namely MIPS architecture , and MIPS performance .
The MIPS stands for “ M icroprocessor without I nterlocked P ipeline S tages”
based on the hardware architecture originally pioneered in 1980s by Stanford University; the elegance of MIPS is based on a single-cycle machine with Reduced Instruction Set Computer (RISC). The RISC instruction set means less-numbers, and simple type of instructions compared to more-numbers and complex-type, C omplex I nstructions S et C omputer.
RISC architecture is recognized as ‘load’ and ‘store’ architecture as well, where simple instructions are required to execute complex operations like multiplication of 2 × 4 could be achieved by adding 2 + 2 + 2 + 2.
A quick example of 75 instructions in PIC18F verses well over 200 instructions of R32C or STAR12
MIPS performance measurement matrix is completely a different parameter. It is a method of evaluating speed of the processing architecture based on a simple cal-culation, where number of instructions are divided by the execution-time and then multiplied by million. So, if a CPU is executing one million instructions per second then it could be defi ned in MIPS term as MIPS rated speed of 1. Likewise a CPU executing one thousands instruction per second means it is at MIPS rated speed of 0.001. So, the MIPS stands for Million Instructions per Second.
In the domain of automotive computing, where real time tasks are essential and at times critical for the module operational needs many factors govern the comput-ing performance. These factors include an architectural difference of Harvard verses Von Neumann, pipelined verses no-pipelining, CISC verses RISC, RTOS verses no-RTOS, and range of many other software architectural design factors that makes a difference in the overall throughput of computing.
So, keep in mind that MIPS measurement-matrix is not the true measurement criterion across all platforms of microcontrollers; rather it is just one factor that could be counted. 1