Multi-Row Cells

In Section 5.3, we describe BONNCELL’s method to generate transistor-level

layouts spanning several circuit rows. In practice, this feature is most often activated by the user when the surroundings of the cell dictate another form factor. However, it can also be used to handle very large cells and, in general, produces variants of the default layouts, thereby increasing the chance to find feasible routings. To evaluate the feature, we configured each of the 102 CLC

cells to be laid out within 1, 2, and 3 circuit rows.

The Tables 7.5 and 7.6 show the results of these experiments. The first table summarizes the results of the 63 cells on which no timeout occurred in the single-row case, i.e. provably optimal layouts are known for this case. As it turns out, the multi-row runs did not end with a timeout either on these 63 cells. The second table provides the same statistics for the 39 remaining cells with a timeout. Using 2 rows, only 11 of those encountered a timeout, and with 3 rows only a single cell did not finish within the time limit of 2 hours. The first table suggests that it rarely pays off to generate multi-row layouts when an optimal single-row version is available. The area covered by the cell’s rectangular outline increases, on average, by 29% for 2 rows and by 56% for 3 rows. Not a single multi-row cell is smaller than the minimum- width solution in a single row. In principle this would be possible, because arranging the layouts of the individual rows side by side might require ad- ditional empty tracks between those blocks due to minimum distance rules. However, considering those 63 CLCcells, the single-row variants are always

the most compact ones. When the single-row placement fails, this behavior changes. Table 7.6 shows that in some cases the cell area decreases. If for every cell the smallest variant is chosen, netlists can be laid out with 10% less area on average.

The netlength values in the tables are, in this case, the sum of vertical and horizontal total netlengths. In contrast to the single-row problem, where the vertical netlength is largely fixed and not subject to optimization, we now have a 2-dimensional problem in which both dimensions of the netlengths are relevant. Comparing against non-optimal single-row placements, the multi-row counterparts, which are also non-optimal, can have a significantly

Table 7.5: Multi-row results on the 63 CLCcells that were successfully placed within one circuit row without a timeout. The last column shows the results obtained by taking for each cell the number of rows that produces the best value for the given measure.

Number of rows

1 row 2 rows 3 rows Best Change in cell area (avg) — +29% +56% +0% Change in total netlength (avg) — +17% +33% -2% Sum of total netlengths 15 280 16 900 19 088 — NLg(Λ)(min/median/max) 0/20/82 0/18/76 0/16/64 —

Sum of gate netlengths 1 538 1 422 1 298 1 188 Sum of placement runtimes 16 870 147 2 335 112

Number of timeouts 0 0 0 0

Successful routings 89% 81% 62% 90%

Table 7.6: Same as Table 7.5, but for the 39 CLC cells for which a timeout occurred in the single-row placement.

Number of rows

1 row 2 rows 3 rows Best

Change in cell area (avg) — -2% +19% -10%

Change in total netlength (avg) — -28% -22% -28% Sum of total netlengths 37 973 24 458 26 889 — NLg(Λ)(min/median/max) 24/190/938 18/70/262 18/66/152 —

Sum of gate netlengths 10 694 3 686 2 674 2 536 Sum of placement runtimes 280 800 168 774 60 006 54 536

Number of timeouts 39 11 1 1

Successful routings 36% 49% 46% 64%

better netlength. Increasing the number of rows also tends to improve the gate netlength, which is clear because now more FETs may share the same x-coordinate (however, the transistors are usually assigned so that all FETs sharing a gate contact lie within the same circuit row).

As the multi-row placement does not perform an exhaustive search over all possible assignments of FETs to circuit rows, it does not guarantee to find a global optimum. Only after such an assignment has been fixed, optimal lay- outs are computed within the individual circuit rows. These can be found much faster than in the single-row case because much fewer FETs are con- tained in each given row. For this reason, multi-row placements are usually finished much faster, which also reflects in the tables. Using two rows, all instances in the first group can be laid out in a total runtime of 147 seconds.

7.2. EVALUATION OF BONNCELL FEATURES 121

Figure 7.7: The same netlist laid out in 1, 2, and 3 circuit rows.

In addition to the placement’s behavior, we evaluated the routability of the layouts. The experiments confirm the trend that with an increasing number of rows the probability to find a routing decreases, which is explained by the added difficulty to route nets through the border regions between circuit rows. When no optimal single-row placement could be found, the multi-row variants—especially those without a timeout—have a higher probability to be routable. For 25 out of the 39 cells in this group one of the three variants was successfully routed. In total, 82 out of all 102 CLCcells were routable in

Table 7.7: Placement runtime, layout width, gate netlength, total netlength, and routability with default settings and with mixed FET rows activated. The last column group shows the differences to the default results. If no runtime is given, a timeout occurred.

FET Areas Default layout Mixed FET rows

Cell n p Runt. W NLg NL Rtb.3 Runt. W NLg NL Rtb.3

clc26 11 34 0.0 13 6 51 yes 0.1 -2 +14 -2 yes clc46 28 10 0.0 14 34 114 no 1.5 -1 -6 -14 no clc59 288 112 — 79 530 1 774 no — 0 0 0 no clc62 94 34 — 26 50 242 yes — +3 +74 +84 yes clc64 120 41 — 40 158 541 yes — 0 0 0 yes clc65 26 9 0.0 9 10 51 yes 0.0 0 0 0 yes clc80 12 5 0.0 7 0 52 yes 0.0 0 0 0 yes clc85 180 60 2.4 27 42 301 no — 0 0 0 no clc89 6 22 0.0 8 6 29 yes 0.1 0 0 0 yes clc94 219 9 — 54 74 1 048 yes — +24 +52 +577 yes