5 Management Function Table of Contents
7.3 Protection Settings
7.3.11 Negative Sequence Overvoltage Protection Settings
The negative sequence overvoltage protection settings (in the submenu “NegOV Settings”) are used to determine the characteristic of the negative sequence overvoltage protection.
All the settings of the negative sequence overvoltage protection are listed in the following table.
No. Menu text Explanation Range Step
1 59Q.U2_Set The voltage setting of the negative sequence
overvoltage protection 2~120V 0.001V
2 59Q.t_Op The time setting of the negative sequence
overvoltage protection 0~100s 0.001s
3 59Q.En The logic setting of the negative sequence
overvoltage protection 0~1 1
4 59Q.OutMap The output matrix setting of the negative sequence overvoltage protection
0x00000000 ~ 0x7FFFFFFF 1
7.3.12 Zero Sequence Overvoltage Protection Settings
The zero sequence overvoltage protection settings (in the submenu “ROV Settings”) are used to determine the characteristic of the zero sequence overvoltage protection.
All the settings of the zero sequence overvoltage protection are listed in the following table.
No. Menu text Explanation Range Step
1 59G1.3U0_Set The voltage setting of the stage 1 zero sequence
2 59G1.t_Op The time setting of the stage 1 zero sequence
overvoltage protection 0~100s 0.001s
3 59G1.En The logic setting of the stage 1 zero sequence
overvoltage protection 0~1 1
4 59G1.OutMap The output matrix setting of the stage 1 zero sequence overvoltage protection
0x00000000 ~ 0x7FFFFFFF 1 5 59G2.3U0_Set The voltage setting of the stage 2 zero sequence
overvoltage protection 2~160V 0.001V
6 59G2.t_Op The time setting of the stage 2 zero sequence
overvoltage protection 0~100s 0.001s
7 59G2.En The logic setting of the stage 2 zero sequence
overvoltage protection 0~1 1
8 59G2.OutMap The output matrix setting of the stage 2 zero sequence overvoltage protection
0x00000000 ~ 0x7FFFFFFF 1
7.3.13 Frequency Protection Settings
The frequency protection settings (in the submenu “FreqProt Settings”) are used to determine the characteristic of the frequency protection.
All the settings of the frequency protection are listed in the following table.
No. Menu text Explanation Range Step
1 81.Upp_VCE The setting of the low voltage blocking element of
the frequency protection (phase-to-phase voltage) 10~120V 0.001V 2 81U1.f_Set The frequency setting of the stage 1
under-frequency protection 45~60Hz 0.001Hz
3 81U1.t_Op The time setting of the stage 1 under-frequency
protection 0~100s 0.001s
4 81U1.En The logic setting of the stage 1 under-frequency
protection 0~1 1
5 81U1.OutMap The output matrix setting of the stage 1 under-frequency protection
0x00000000 ~ 0x7FFFFFFF 1 6 81U2.f_Set The frequency setting of the stage 2
under-frequency protection 45~60Hz 0.001Hz
7 81U2.t_Op The time setting of the stage 2 under-frequency
protection 0~100s 0.001s
8 81U2.En The logic setting of the stage 2 under-frequency
protection 0~1 1
9 81U2.OutMap The output matrix setting of the stage 2 under-frequency protection
0x00000000 ~ 0x7FFFFFFF 1 10 81U3.f_Set The frequency setting of the stage 3
under-frequency protection 45~60Hz 0.001Hz
11 81U3.t_Op The time setting of the stage 3 under-frequency
12 81U3.En The logic setting of the stage 3 under-frequency
protection 0~1 1
13 81U3.OutMap The output matrix setting of the stage 3 under-frequency protection
0x00000000 ~ 0x7FFFFFFF 1 14 81U4.f_Set The frequency setting of the stage 4
under-frequency protection 45~60Hz 0.001Hz
15 81U4.t_Op The time setting of the stage 4 under-frequency
protection 0~100s 0.001s
16 81U4.En The logic setting of the stage 4 under-frequency
protection 0~1 1
17 81U4.OutMap The output matrix setting of the stage 4 under-frequency protection
0x00000000 ~ 0x7FFFFFFF 1 18 81O1.f_Set The frequency setting of the stage 1
over-frequency protection 50~65Hz 0.001Hz
19 81O1.t_Op The time setting of the stage 1 over-frequency
protection 0~100s 0.001s
20 81O1.En The logic setting of the stage 1 over-frequency
protection 0~1 1
21 81O1.OutMap The output matrix setting of the stage 1 over-frequency protection
0x00000000 ~ 0x7FFFFFFF 1 22 81O2.f_Set The frequency setting of the stage 2
over-frequency protection 50~65Hz 0.001Hz
23 81O2.t_Op The time setting of the stage 2 over-frequency
protection 0~100s 0.001s
24 81O2.En The logic setting of the stage 2 over-frequency
protection 0~1 1
25 81O2.OutMap The output matrix setting of the stage 2 over-frequency protection
0x00000000 ~ 0x7FFFFFFF 1 26 81O3.f_Set The frequency setting of the stage 3
over-frequency protection 50~65Hz 0.001Hz
27 81O3.t_Op The time setting of the stage 3 over-frequency
protection 0~100s 0.001s
28 81O3.En The logic setting of the stage 3 over-frequency
protection 0~1 1
29 81O3.OutMap The output matrix setting of the stage 3 over-frequency protection
0x00000000 ~ 0x7FFFFFFF 1 30 81O4.f_Set The frequency setting of the stage 4
over-frequency protection 50~65Hz 0.001Hz
31 81O4.t_Op The time setting of the stage 4 over-frequency
protection 0~100s 0.001s
32 81O4.En The logic setting of the stage 4 over-frequency
protection 0~1 1
33 81O4.OutMap The output matrix setting of the stage 4 over-frequency protection
0x00000000 ~ 0x7FFFFFFF 1
34 81R.dt_Set The cycle number for the calculation of the
frequency rate-of-change protection 3~8 1
35 81R1.df/dt_Set The setting of the stage 1 frequency
rate-of-change protection -10~10Hz/s
0.001 Hz/s 36 81R1.f_Pkp The pickup frequency setting of the stage 1
frequency rate-of-change protection 45~65Hz 0.001Hz 37 81R1.t_Op The time setting of the stage 1 frequency
rate-of-change protection 0~100s 0.001s
38 81R1.En The logic setting of the stage 1 frequency
rate-of-change protection 0~1 1
39 81R1.OutMap The output matrix setting of the stage 1 frequency rate-of-change protection
0x00000000 ~ 0x7FFFFFFF 1 40 81R2.df/dt_Set The setting of the stage 2 frequency
rate-of-change protection -10~10Hz/s
0.001 Hz/s 41 81R2.f_Pkp The pickup frequency setting of the stage 2
frequency rate-of-change protection 45~65Hz 0.001Hz 42 81R2.t_Op The time setting of the stage 2 frequency
rate-of-change protection 0~100s 0.001s
43 81R2.En The logic setting of the stage 2 frequency
rate-of-change protection 0~1 1
44 81R2.OutMap The output matrix setting of the stage 2 frequency rate-of-change protection
0x00000000 ~ 0x7FFFFFFF 1 45 81R3.df/dt_Set The setting of the stage 3 frequency
rate-of-change protection -10~10Hz/s
0.001 Hz/s 46 81R3.f_Pkp The pickup frequency setting of the stage 3
frequency rate-of-change protection 45~65Hz 0.001Hz 47 81R3.t_Op The time setting of the stage 3 frequency
rate-of-change protection 0~100s 0.001s
48 81R3.En The logic setting of the stage 3 frequency
rate-of-change protection 0~1 1
49 81R3.OutMap The output matrix setting of the stage 3 frequency rate-of-change protection
0x00000000 ~ 0x7FFFFFFF 1 50 81R4.df/dt_Set The setting of the stage 4 frequency
rate-of-change protection -10~10Hz/s
0.001 Hz/s 51 81R4.f_Pkp The pickup frequency setting of the stage 4
frequency rate-of-change protection 45~65Hz 0.001Hz 52 81R4.t_Op The time setting of the stage 4 frequency
rate-of-change protection 0~100s 0.001s
53 81R4.En The logic setting of the stage 4 frequency
rate-of-change protection 0~1 1
54 81R4.OutMap The output matrix setting of the stage 4 frequency rate-of-change protection
0x00000000 ~ 0x7FFFFFFF 1