NMOS Subthreshold LVT

The same test bench was then used to perform the same geometric sweeps for an NMOS LVT device at 250mV (VT = 314mV). This data may be s een in Figures 8, 9 and 10.

Figure 8 shows that the dopant density increase imparted by the HALO implants, in comparison to the background retrograde doping profile of the channel, is greater in the LVT NMOS device than in the RVT device. For this reason, the RSCE is comparatively stronger than the SCE and therefore has a greater influence on the geometric drain current response in the LVT device. In the SS corner, the SCE is all but suppressed, with the drain current increasing as the device length increases, eventually peaking and

diminishing when the channel center reaches the background channel dopant density. The INWE provides a similar relationship as in the RVT device, with the effect relatively suppressed in the SS corner due to the added effort required to invert the channel. In the TT corner, the SCE is slightly stronger, but the RSCE still dominates. There is a sharp rise in drain current from minimum to 100nm, then a gradual but clear fall off as the channel center reaches the background channel dopant density. The INWE is more pronounced, with an observable increase in drain current as the device width tends towards minimum.

In the FF corner, the RSCE is still present, but the SCE has started to dominate. The INWE effect is clearly pronounced with an appreciable increase in drain current as the device width tends towards minimum.

Figure 9 shows the LVT leakage characteristics across the three process corners. The SS corner shows a greatly subdued RSCE response and SCE beginning to dominat e at larger channel width. The INWE is rather negligible like the drive current response.

The TT corner shows the SCE starting to dominate more of the width. The devices around the minimum width however are still dominated by the RSCE. The INWE is more prevalent with greater deviation in the linearity of the width response and slight increases in leakage current around the minimum width.

The FF corner shows vestiges of the RSCE, but the SCE has started to dominate the entire width. The INWE is clearly visible with considerable increase in leakage current as the width tends towards minimum.

Similar trends across corners are observed in the LVT as were observed in the RVT device. The RSCE is most prominent in the SS corner and least prominent in the FF corner. The INWE is most prominent in the FF corner and least prominent in the SS corner. The TT corner offers the balance between these two trends.

By comparison to the RVT NMOS device, the RSCE is more prominent in the LVT device owing to the increase in proportionality of the HALO dopant density to that of the background channel. Conversely the INWE is more subdued. This may be down to

several processing parameters. However the most likely culprit is change in the surface state potential and flat-band voltage (Section 2.7.3), both of which are derived from the dopant densities. Figure 10 shows the data processed into the geometric Ion/Ioff sweeps. The SS corner shows the same overall trend as the RVT device. The greater dominance of the SCE in the leakage current characteristic has the effect of lowering the Ion/Ioff ratio as the device length tends towards minimum. However, unlike the corresponding SS RVT sweep, the dominance of the RSCE in the drive current interrupts this trend considerably, producing a kink in the response until the INWE dips into the minimum length/width device. The INWE effect is less prominent as the width increases, as would be expected. The TT corner shows a similar trend due to the comparative influence the SCE has on the leakage current over the drive current. There is less interruption from the RSCE as its influence is less than in the SS corner. The INWE effect is more prevalent as the lift visible at minimum width in the SS corner is missing in the TT corner.

Finally in the FF corner, the influence of the RSCE has all but faded, leaving only the characteristic roll-off of due to the SCE. The effect of the INWE is greatest with a clear dip in the Ion/Ioff ratio at minimum width owing to its greater influence on the leakage current. The same overall trends are observed as in the NMOS device. The SCE affects the leakage current greater than the on current, degrading the Ion/Ioff ratio towards minimum length. However in the LVT case there is noticeable interruption due to the influence of the RSCE on the on current. The process dependence is the same, with a higher proportional degradation in the fast corner. The INWE has a similar greater influence on leakage current, resulting in degradation in the Ion/Ioff ratio at minimum device width and is most prominent in the fast corner. Important to note is the absolute magnitudes of the Ion/Ioff ratio in comparison to the RVT device and process corner to corner. The lower dopant density in the channel affects the leakage current greater than the on current. The result is that the Ion/Ioff ratio of a TT RVT device is around 2000 for an RSCE aware length and minimum width, whilst the same device in LVT has an Ion/Ioff ratio of only 1300. This effect is clearly visible as the process corners progress towards the fast corner with the lowest channel dopant density, with the Ion/Ioff ratio falling off to around 700. This indicates a design consisting purely of LVT devices may perform faster than one consisting purely of RVT devices, but that the performan ce-to- leakage ratio and therefore overall energy consumption will be considerably worse. Moreover this would have a significant impact on circuit topology, restricting designs with parallel transistors.