Propagation Delay

As discussed in the previous subsection, performance is inherently dependent on device propagation delay. This is influenced by both the device’s ability to sink/source current and device capacitances. Whilst both of these metrics have been independently explored based on their variation under subthreshold physical effects, the actual propagation delay may be directly simulated using a simple FO4 inverter test bench. Once again this test bench is based upon a sample test bench outlined in Harris and Weste [82]. Figure 35 shows a schematic for the test bench.

Figure 35: Propagation delay SPICE test bench

The two input stages prior to the DUT shape the input transition to the DUT, reducing the dependence of the DUT’s transition characteristics on the source step function. Two stages follow the DUT in order to provide a realistic load.

To determine a reliable evaluation on propagation delay, rising and falling delays are measured and the two cases averaged to generate an average propagation delay. The measurement is triggered for a rising propagation delay from node c crossing the 50% VDD boundary and measured as node d crosses the 50% VDD boundary on the

corresponding fall transition on the output. The falling propagation delay is measured for the complementary transitions.

Both the P and N devices are geometrically swept in an identical simultaneous fashion, resulting in a constant P-to-N ratio of 1:1 for all test cases. Sweeps were created for both LVT and RVT devices at all three process corners. Figure 36 shows the results for the LVT devices.

Figure 36 shows the average propagation delay geometry sweep for the LVT SS device at a temperature of 25°C and a supply voltage of 250mV. Both the PMOS and NMOS SS device drive current responses showed a significant and clear increase from minimum length due to the RSCE. The limited effect of the INWE showed a strong current response in response to increasing width. The gate capacitance response shows a linear proportionality to the quadrature of the device. These effects combine to show a clear decrease in propagation delay from minimum length, with the minimum delay at 230nm. With the exception of the minimum length, the response also shows a slight decrease as the device width tends to minimum. The optimal device sizing for minimum delay is therefore 230nm length, minimum width devices. Interestingly, due to the linear capacitance relationship with width and the increasing width related drive current response, the gain in current is offset by the additional capacitance of the load and the propagation delay remains fairly flat over device width.

A minimum width device therefore provides the same performance as a large width device, with the additional benefits of smaller silicon area and dynamic power reduction due to lower gate capacitance.

Figure 36 also shows the average propagation delay geometry sweep for the LVT TT device at a temperature of 25°C and a supply voltage of 250mV. Both the PMOS and NMOS TT device drive current responses showed a mixture of SCE and RSCE. This is reflected in the propagation delay response where there is a sight inflection at minimum length, but ultimately the RSCE dominated, with the lowest propagation delay occurring at 150nm. The INWE current deviation in the width for both underlying devices was more apparent, and is therefore more apparent in the propagation delay response, with a clear decrease as device width tends towards minimum. Again, the optimal device sizing is therefore larger than minimum length and minimum width.

Finally the figure also shows the geometry sweep for the FF corner at the same PVT parameters. In the underlying device physics, the SCE completely dominated the drive current responses. This is shown in the propagation delay response, where the minimum propagation delay actually occurs at minimum length. The underlying physics also showed the fast corner to be most influenced by the INWE. This again is evident in the propagation delay response, where the delay reduces greatly as the width tends towards minimum. The optimal device s izing is therefore minimum length, minimum width. In reality, in the subthreshold regime, the variation would likely see these devices upsized

from minimum length anyway. This shall be discussed later in the section on device variation.

The same test bench was used to perform the same geometry sweeps for the RVT devices. Figure 37 shows the results of these simulations.

Figure 37 shows the average propagation delay geometry sweep for the RVT SS device at a temperature of 25°C and a supply voltage of 250mV. Both NMOS and PMOS devices at this PVT point showed width dependent response to length change in their drive current responses, i.e. the dominance of SCE/RSCE depended on the width. At minimum width, the RSCE dominated. As width increased, the SCE began to dominate. This is reflected in the propagation delay response. At minimum width, the optimal length is 200nm. As the width is increased, the optimal length decreases, eventually reaching minimum length. Due to the complex nature of the RSCE/SCE interaction, the INWE is interrupted at minimum width by the dominance of the RSCE. Other than the minimum width, minimum length point, the INWE dominates and the propagation delay decreases as width tends towards minimum. The optimal device sizing for this gate is therefore variant. The highest current per unit area and therefore performance is achieved at minimum width, 200nm length. Changes in device width would require a corresponding reduction in length to maintain the optimal value.

The figure also shows the RVT TT device at the same PVT point. Both the underlying devices show muted RSCE and slight dominance of the SCE. This is reflected in the propagation delay response, where the length response is fairly monotonic, decreasing towards minimum length. There is a slight RSCE behavior at minimum width, giving a propagation delay at minimum at 100nm length for minimum width. As the width increases, the optimal length quickly tends towards the device minimum. The INWE affects both underlying devices and is therefore apparent in the propagation delay response, giving a minimum propagation delay at minimum width for all lengths above the 100nm optimal point. Accepting the variation limitation in length, the optimum sizing for this device is therefore minimum width, 100nm length. Should the width be increased, the length would have to be decreased towards minimum length as much as variation would allow.

Finally the figure also shows the RVT FF device at the same PVT point. The SCE dominates the length response of the underlying devices and therefore, the propagation delay is lowest at minimum length for all widths. The INWE dominates the width response of the underlying devices at minimum width. The propagation delay therefore falls off monotonically towards minimum width. The optimal sizing strategy for this device is therefore minimum width and as close to minimum length as variation allows.

When the results are examined in their entirety, there are a few trends that may be observed. The first is that the optimal sizing strategy varies between the LVT and RVT devices. The LVT devices are more affected by RSCE. This translates into an increase their optimal device length. As the device length corresponds to a possible increase in cell width, the LVT devices will inherently generate larger cell footprints and therefore occupy a larger silicon area than designs synthesized from the RVT devices.

The second trend is that the process corner affects the RSCE, and therefore the slower the process corner, the larger the optimal length and corresponding cell footprint. Whilst the underlying silicon received from the fabrication house is beyond the control of the designer, the choice of process targeting strategy is. This is discussed later in the design sections.

The third trend is that the INWE affects the propagation delay in all devices and corners. For devices above 90nm in length (the minimum length considered safe for v ariation) the minimum propagation delay always occurs at minimum width. Utilizing the

parallelization techniques outlined earlier, the current per unit width and therefore performance will always be maximized using minimum width devices. The cost of this strategy however is the related increase in leakage current.