Hardware Description
CPU:
8086 is a 16 bit, third generation microprocessor and is suitable for an exceptionally wide spectrum of microcomputer applications. This flexibility is one of most outstanding characteristics.
8086 has got 16 data lines and 20 address lines. The lower 16 address lines are multiplexed with 16 data lines. Hence it becomes necessary to latch the address lines. This is done by using 74 LS 373. In fact several of the 40 CPU pins have dual functions that are selected by a strapping pin. In this kit 8086 is used in the max. mode (MN/MX input held logically low). The 8088 is designed with an 8-bit external path to memory and I/O. Except that the 8086 can transfer 16 bits at a time, the two processors & software are identical in almost every respect. Software identical in almost every respect. Software written for one CPU will execute on the other without alteration. The two processors are designed to operate with the 8089 I/O processors and other processors in multiprocessing and distributed processing systems.
The INTR, TEST & Hold Inputs to 8086 are pulled down and are brought out at PCB FRC connector.
The mask able interrupt INTR is available to the peripheral circuits through the expansion Bus. To use the mask able interrupt an interrupt vector pointer must be provided on the data bus when INTA is active. An interrupt Controller Circuit is provided to take care of more than one source of interrupt.
Co-Processor 8087:
The 8087 Co-processor ―hooks‖ have been designed into the 8086 and 8088 so that these types of processor can be accommodated in the future. A co-processor differs from an independent processor in that it obtains its instructions from another processor, called a host. The co-processor monitors instructions fetched by the host and recognizes certain of these as its own and executes them. A co-processor, in effect, extends the instruction set of its host computer.
I/O Processor 8089:
The 8086 and 8088 are designed to be used with the 8089 in high performance I/O applications. The 8089 in conceptually resembles a microprocessor with two DMA channels and an instruction set specifically tailored for I/O operations. Unlike simple DMA controllers, the 8089 can service I/O devices directly, removing this task from the CPU. In addition, it can transfer data on its own bus or on the system bus, can match 8-bit or 16-bit peripherals to 8-bit or 16-bit buses, and can transfer data from memory to memory and from I/O devices to I/O device. 8089 has been used here in local mode. The system bus, can match 8-bit or 16-bit peripherals to 8-bit or 16-bit buses, and can transfer data from memory to memory and from I/O devices to I/O device. 8089 has been used here in local mode. Clock Generation:
The clock generator circuit is an Intel‘s 8284 clock generator/driver. The circuit accepts a crystal input which operates at a fundamental frequency of 6.144 MHz. (6.14 MHz was selected since this frequency is a multiple of the baud rate clock and also provides a suitable frequency for the CPU). The clock generator/driver divides the crystal frequency by three to produce the 2MHz CLK signal required by the CPU. Additionally, the clock generator performs a further divide-by-two output called PCLK (peripheral clock) which is the primary clock signal used by the remainder of the circuits.
The clock generator/driver provides two control signal outputs which are synchronized (internally) to the 2 MHz CLK signal; RDY (ready) and RST (reset). RST is used to reset the Nvis 5586A to an initialized state that occurs when the RES input goes low (when power first is applied or when the SYSTEM RESET key is pressed). The RDY output is active (logically high) when the RDY 1 input from the wait state generator is active. As will be explained in the next section, the RDY 1 input is active whenever onboard memory is addressed or when a selected number of ―wait states‖ occurs.
The system can operate at either 2 MHz or 1 MHz. This is selected by a set of jumpers JP3 on the right hand side of the 8284 clock generator as shown below:
1. 2 MHz (UPPER) 2. CLK
3. 1 MHz (LOWER)
The Nvis 5586A is supplied in 2 MHz configuration. Bus Controller:
The 8288 is a Bus Controller which decodes status signals output by an 8089, or a maximum mode 8086. When these signals indicate that the processor is to run a bus cycle, the 8288 issues a bus command that identifies the bus cycle as memory read, memory write, I/O read, I/O write, etc. It also provides a signal that strobes the address into latches. The 8288 provides the drive level needed for the bus control lines in medium to large systems.
Memory:
Nvis 5586A provides 128K Bytes of EPROM loaded with monitor and 32K bytes of CMOS RAM. The total onboard memory can be configured as follows:
EPROM - 128K Bytes of EPROM using two 27C512. RAM - 32K Bytes of RAM.
The system provides two 28 Pin sockets for the EPROM area named as EVEN-ROM & ODD- ROM and two 28 Pin sockets for the RAM area named as EVEN-RAM & ODD-RAM. EVEN-ROM & ODD-ROM can be defined to have EPROM 27512.
With the 20 bit address of 8086, a total of 1 Mega Bytes of memory can be addressed with the address slot as 00000 to FFFFF. Although the total onboard memory capacity is 180K Bytes 128K Bytes of EPROM and 32K Bytes of RAM.
8255:
8255 is a programmable peripheral interface (PPI) designed to use with 8086 Microprocessor. This basically acts as a general purpose I/O component to interface
peripheral equipments to the system bus. It is not necessary to have an external logic interface with peripheral devices since the functional configuration of 8255 is programmed by the system software. It has got three input/output ports of 8 lines each (PORT-A, PORT- B and PORT-C). Port-C can be divided into two ports of 4 lines each named as Port-C upper and Port-C lower. Any Input/Output combination of Port-A, Port-B, Port-C upper and Port- C lower can be defined using the appropriate software commands. The Port addresses for these ports are given here. Nvis 5586A provides nine Input/Output ports of 8 lines each using three 8255 chips. These ports are brought out at connectors.
8253:
This chip is a programmable interval timer/counter and can be used for the generation of accurate time delays under software control. Various other functions that can be implemented with this chip are programmable rate generator. Event Counter, Binary rate multiplier, real time clock etc. This chip has got three independent 16 bit counters each having a count rate of up to 2 MHz. The CLK, GATE & OUT signals of these timers are brought out at the connector.
8251:
This chip is a programmable communication interface and is used as a peripheral device. This device accepts data characters from the CPU in parallel form and then converts them into a continuous serial data stream for transmission. Simultaneously it can receive serial data stream and converts them into parallel data characters for the CPU. This chip will signal the CPU whenever it can accept a new character for transmission or whenever it has received a character for the CPU. The CPU can read the complete status of it at any time. 8251 has been utilized in Nvis 5586A for RS-232-C serial interface.
8259:
The 8259 is a device specifically designed for use in real time, interrupt driven microcomputer systems. It manages eight levels of requests and has built in features for expandability to other 8259‘s. It is programmed by system‘s software as an I/O peripheral. A selection of priority modes in which the requests are processed by 8259 can be configured to match his system requirements. The priority modes can be changed or reconfigured dynamically at any time during the main program.
Battery Backup:
The Nvis 5586A provides a battery backup for the onboard RAM area using 3.6V Ni-Cd Rechargeable battery. Nvis 5586A has facility for connecting +5V to the RAM area if the Ni-Cd battery fails. The selection for +5V or Battery supply Jumper (JP2).
Display:
This display contains 2 lines and each line consists of 20 words (20x2). This is a cursor LCD display modular. The CPU receives each 8 bits letter which is locked into the internal display data of RAM (data display of RAM 80 bytes (D.D.RAM) allows 80 characters to be stored), and transfer to 5x7 dot of array word and appear on the displayed.
This LCD modular contains the word generator ROM that will supply 160 different 5x7 dot of array word and also a 64 bytes word generator RAM. Users can define 8 types 5x7 dot of array word.
The position of word display goes into the LCD Modular through the data bus in CPU. Next through the instruction register and finally write the words into the data register to display on a specific location. The LCD Modular will automatically increase or decrease the words in order to move to different addresses. The user can therefore continue sending in word code. The cursor as to moved around or moved in the right of left direction.
Specification of Display :
Display data RAM : 80 x 8 BLT (80 words) Character generator ROM : 160 of 5x7 dot of array word
Character generator RAM : 8 different users programmed 5x7 dot of array
Kinds of instructions : Clear the display, send cursor home (HOME), ON/OFF display. Cursor ON/OFF, character blinking cursor move to another position, display change position. When the internal power is on, the circuit is reset.
Functional Block Diagram
Note: Some models incorporate a temperature compensation circuit within the bias voltage generator.
The LCD0. modular has 2, 8-bits register-one instruction register (IR) and one data register (DR).
The instruction register stores the instruction code and address information, which contains display data RAM and address of character generator RAM. However, the content of IR is only for read-in but not read-out.
The data register can only temporary store data, the input data first goes through LCD and is stored in the data register. It will then automatically be transferred to display data RAM or character generator RAM. When the CPU read the data from the displayed RAM or from the
character generator RAM, it wills also temporary store the data in the data register. When the address information is input into the instruction register, the relative data will be moved from display register RAM or character generator RAM to the data register. Then the data can be read from data register by using the output instruction of CPU.
One way to select the two registers is to select the register signal (RS) like follow: RS R/W Function
0 0 Data Bus —> instruction Register
0 1 Read out busy flags (BUSY FLAG DB7) and address counter (DB0-DB6)
1 0
Input into data register and execute the inner instruction: (D.R.RAM— > D.R.
OR C.G.RAM — D.R.)
1 1
Get the data out from register, and execute the inner instruction: (D.D.RAM—> D.R.
OR C.G.RAM—> D.R.) Busy Flag (B.F.):
When busy flag is ―1‖, it indicates that the LCD Modular is executing the inner instruction and no other instruction can be accepted. The LCD Modular can only accept information when BF is lower to ―0‖.
Address Counter (A.C.):
The address counter is used to count the display data RAM, or address of character generator RAM. When the address setting instruction address will be sent into the address counter. When the data is sent into or read out from display register RAM or from the character generator RAM, the address counter will automatically add or subtract 1.
When the content of address counter is in RS = 0 and R/W = 1, the output data line is DB0 DB6.
Display Data RAM (D.D. RAM):
This is an 80x8 bit RAM, which can store 80 8-bit character codes as the display data; it can be sent to CPU as the RAM data section without going through RAM section.
Address setting of data display RAM is as followed:
High level bus Low level bus AC6 AC5
AC4
AC3 AC2 AC1 AC0 Data displays RAM and display position of LCD is as followed: Character Position: 1 2 3 4 5 6 7 8 9 10 11…19 20
(Decimal)
First Line: 00 01 02 03 04 05 06 07 08 09 0A..16 17 (Hexadecimal)
Second Line: 40 41 42 43 44 45 46 47 48 49 4A...56 57 (Hexadecimal)
Character Generator ROM (C.G. ROM):
This ROM generates 5x7 dot of array character has 160 different 8-bit character code. The shape and code are shown in Table 2 and 3.
Character Generator RAM (C.G.RAM):
This RAM stores 8 different 5x7 dot of array character which allows the user to design the program. When the character codes are stored in the C.G.RAM, which are the same as the characters in Table 2 and 3, they will be sent to display data RAM. The display data and characters are shown in Table 4.
Timing Generator:
Character Codes:
Note:
1. The CG RAM generates character patterns in accordance with the user‘s program.