Optimisation of JFET width

The optimisation process for the power VD-MOSFET was carried out using the finite element simulation software SILVACO. To find out the optimum JFET width for the power VD-MOSFET structure, the JFET width was varied from 1 µm to 10 µm in the simulation. Since the lateral dimensions (i.e. widths of the channel, JFET and cell pitch regions) are the same for all 1 kV, 3.3 kV and 10 kV VD-MOSFETs design, the simulation was performed on a 1 kV rating VD-MOSFET structure and the results were apply to the 3.3 kV and 10 kV VD-MOSFETs design. The computation time for simulation 1 kV device was greatly reduced compare to 10 kV device because of the much thinner drift region and much lower number of mesh points required for reliable results.

Figure 3.8 shows the numerical simulation for 1 kV VD-MOSFET structure when the JFET region width is increased from 1 to 10 µm while keeping the window size from P+

region to the edge of P-body the same. A gate bias of 20 V and drain source voltage of

Figure 3.8: Simulation result of specific on-state resistance for 1 kV shielded planar VD-MOSFET with different width of JFET region.

1.5 V was used in this plot. Figure 3.9 to 3.11 show the impact of different width of the JFET region on the specific on-resistance for the 1 kV, 3.3 kV and 10 kV shielded planar VD-MOSFET. An inversion layer mobility of 20 cm2_{/V.s was used for this analysis.}

From Figure 3.8 it is seen that there is a low total specific on-resistance for structures with JFET region width in a range of 1 to 2 µm. However, the specific on-resistance increases sharply if the JFET region width is less than 1 µm and beyond 5 µm. The resistance of the JFET region and drift region will increase significantly when the JFET region width is less than 1µm, which leads to increase of total specific on-resistance. From

Figure 3.9: Specific on-state resistance for the 1 kV shielded 4H-SiC shielded planar MOSFET structures from the analytical model calculations.

the analytical model calculations as shown in Figure 3.9 to Figure 3.11, it is seen that the resistance contribution from the channel and accumulation region become dominant when the JFET region width exceeds 10 µm. For 1 kV shielded planar VD-MOSFET, the total specific on-resistance is dominated by the channel resistance which contribute to about 90% of the total on-resistance of the VD-MOSFET as shown Figure 3.9. For the 3.3 kV shielded planar VD-MOSFET, the contribution of the drift region to the total on-resistance has increased close to that of the channel resistance, and the drift resistance will be higher than the channel resistance if the width of JFET region is less than 2µm as shown in Figure 3.10. However, for the 10 kV shielded planar VD-MOSFET the largest contribution to the total on-resistance is the drift region resistance as shown in Figure

Figure 3.10: Simulation result of specific on-state resistance for 3.3 kV shielded planar VD-MOSFET with different width of JFET region from the analytical model

calculations.

3.11.

The two-dimensional numerical simulations of breakdown voltage for the 1 kV shielded planar VD-MOSFET structure is shown in Figure 3.12. It is seen that the breakdown voltage increases when the width of the JFET region is decreased. With JFET region width larger than 8 µm, the breakdown voltage reaches a plateau at 850 V. The improve- ment of breakdown voltage with smaller JFET region can be explained by examination of the potential distribution in the shielded planar VD-MOSFET structure. Figure 3.13 shows the potential distribution for the shielded planar VD-MOSFET with JFET cell pitch width of 10 µm. It can be observed that a depletion region is formed below the P-body region and under the gate oxide region. A crowding of the potential contours

Figure 3.11: Simulation result of specific on-state resistance for 10 kV shielded planar VD-MOSFET with different width of JFET region from the analytical model

calculations.

is observed at location “A” in Figure 3.13, which reduces the breakdown voltage of the device. When the JFET region width is reduced the crowding of the potential contour is also reduced as shown in Figure 3.14 with the JFET region width of 1 µm. From Fig- ure 3.14 it is seen that the reduction of the JFET width in the VD-MOSFET structure can reduce the electric field at the junction, and therefore can support a larger voltage. Therefore in order to have a low on-resistance and acceptable breakdown voltage of the shielded planar VD-MSOFET structure, the JFET region width of 2 µm was chosen for the design for shielded planar VD-MOSFETs (1 kV and 3.3 kV) in this work.

A JFET region doping enhancement is usually required to reduce the on-state resis- tance for high voltage 4H-SiC devices (>5 kV) due to the low doping concentration in the

Figure 3.12: Simulated breakdown voltage of the 1 kV shielded planar VD-MOSFET structure with different JFET region width.

Figure 3.13: Potential contours for the shielded planar VD-MOSFET structure with JFET region width of 10 µm.

Figure 3.14: Potential contours for the shielded planar VD-MOSFET structure with JFET region width of 1 µm.

drift region as discussed in [44]. Although this was not implemented in the fabrication work, numerical simulation have been performed to verify the effect JFET region doping concentration on the breakdown voltage of the VD-MOSFET structure. The enhanced doping concentration was extended to 0.5 µm below the P+ shielding region. The JFET region resistance is related to JFET region doping concentration (NDJ) as discussed in

Chapter 2:

RJFET,sp =

ρJ F ETtP+Wcell

(WJ −2W0)

where the resistivity of the JFET region ρJ F ET is given by

ρJFET=

1 qµnNDJ

(3.17)

Increase the JFET region doping concentration (NDJ) will reduce the resistance of the

JFET region but the increase of charge in this region will degrade the breakdown voltage. Figure 3.15 shows the numerical simulation results on the breakdown voltage of shielded planar VD-MOSFET structure with different JFET region doping concentration. It is seen

Figure 3.15: Breakdown voltage versus JFET doping concentration of 1 kV 4H-SiC shielded planar MOSFET.

that the breakdown voltage decreases linearly as the JFET region doping concentration increases. The breakdown voltage drop is about 20 V as the JFET doping concentration

increase from 2×1016 cm−3 to 1×1017 cm−3. The JFET doping concentration in this case should be close to 2×1016 _cm−3 _{in order to achieve high breakdown voltage.}