Parallel Port Architecture

The parallel port allows print data to be sent from the PC to the printer and data indicating printer status to be received by the PC. This data, sent by the PC, uses eight wires, to transmit a byte of information to the printer. A byte is simply a group of eight bits used together to make a unit of data. Each wire is used to transmit one bit of data at a time. Each bit of data can have one of two possible logic values, 1 or 0. Another nine wires are used to allow the PC to determine the state of the printer and control the flow of data. These nine lines are broken into a set of five input lines and four input/output lines as shown in Figure 2-2.

The physical connection to this port is through a 25-pin connector known as a ‘D25F’ connector (where the ‘D’ refers to the shape of the connector body). The 25 contacts making up this connector are all sockets (female type, hence the ‘F’ in ‘D25F’) which mate with the printer cable connector having 25 pins (male type).

Figure 2-2 Parallel Port Configuration.

The three sets of wires shown in Figure 2-2 show the connection between a PC’s parallel port and an external device, in this case a printer. Each group of wires are controlled, or read, by accessing three sequential locations in the PC’s Input/Output address space, abbreviated to I/O address space. This address space is made up of a number of data storage locations used to allow intercommunication with input/output devices. It is different from the memory generally used by the computer. The PC writes data to particular I/O addresses, where the data is stored and can be accessed by external devices. Other I/O addresses are used to allow external devices to write data into storage for the PC to read, and still other I/O addresses allow bi-directional data transfer.

BASE + 2 BASE + 1 BASE

0 1st _Address

Figure 2-3 I/O Addressing.

The first of the three I/O addresses is referred to as the BASE address as shown in Figure 2-3. It is the lowest address and is used as a reference from which to increment to the other two I/O addresses belonging to the parallel port. Writing to the BASE address will output eight bits of data (a byte) from the parallel port (see Figure 2-2), where each bit uses an individual wire.

Increasing order I/O Addresses Output 8 wires Input 5 wires Input/Output 4 wires

PC (Parallel Port) Printer

BASE Address BASE+1 Address BASE+2 Address

The next address in this block has a numerical value one more than the BASE address, so we label it the BASE+1 address. The BASE+1 address has access to the five input data bits to the PC. This address can only be used to read the state of these five signals.

The third address of this set is labelled the BASE+2 address, being two addresses past the BASE address. This address location is used to control the four bi- directional data bits of the port. Using this address, we can read and write to these four bits.

NOTE

Beware: the four BASE+2 lines used for input and output are NOT ‘strict’ logic outputs. The parallel port interface often has resistors and capacitors connected to these lines to reduce the influence of electrical noise. This causes their states to change much slower than a strict logic output, meaning that erroneous recognition of data can occur when connecting with certain types of logic families.

In addition, due to variation in the individual capacitor values, these signals do not switch at ‘exactly’ the same time (synchronously). This non-synchronous (asynchronous) switching of BASE+2 outputs can cause data transfer problems with data interfaces designed to work synchronously.

Table 2-1 provides a summary of the data bits and D25 connector pins that the parallel port connector uses for each of the three port addresses. Each wire in the cable linking the port to the external device (usually a printer), carries the signal of a particular data bit for that port address. The BASE and BASE+2 addresses have their data bits commencing from D0 upwards. The BASE+1 address, however, starts at data bit D3.

Some data bits used by BASE+1 and BASE+2 addresses are inverted by the parallel port circuitry. These inverted bits are marked by a “ / ” character preceding the letter “D” of that bit. This signal convention is also used on the interface board

schematic diagrams which show detailed electrical interconnections. When using these data bits, the program must compensate for this inversion in order that signals are output from the port or read in through the port as intended.

If a program needs to send a data bit out as a signal through one of the port’s inverted bits, it needs to invert that data bit in software beforehand. This double inversion (once in hardware and again in software) has the effect of correcting the signal back to the intended state. Likewise, when a signal is read through an inverted bit of the port, the now inverted signal must be inverted once more by the program to correct it. The program implements this inversion using one simple line of code, explained in Section 3.6 of the next chapter.

Table 2-1 Parallel Port D25 Connector Pin Assignment. BASE Address

(8-bitoutput data)

BASE +1 Address

(5-bitinput data)

BASE+2 Address

(4-bitinput/output data)

D0 - pin 2 /D0 - pin 1

D1 - pin 3 /D1 - pin 14

D2 - pin 4 D2 - pin 16

D3 - pin 5 D3 - pin 15 /D3 - pin 17

D4 - pin 6 D4 - pin 13

D5 - pin 7 D5 - pin 12

D6 - pin 8 D6 - pin 10

D7 - pin 9 /D7 - pin 11

Note: “/ ” denotes the signal bit is inverted internally by the parallel port circuitry.

D25 pin numbers 18 to 25 are not shown in Table 2-1. They are all connected to the PC electrical ‘ground’ which is connected to the interface board through the interface cable (Figure 2-4). This cable has a D25 male connector at both ends, connected by individual wires in a “one-to-one” arrangement (D25 pin 1 of one connector to the D25 pin 1 of the other connector; likewise for all remaining pins).

Figure 2-4 D25M to D25M Cable.

NOTE

Data bits D0 to D2 of BASE+1 address are not connected to the parallel port circuitry inside the PC. The same holds true for D4 to D7 of the BASE+2 address. Reading these particular bits will produce invalid data.

2 metres