Parameterized Reconfiguration

Parameterized Reconfiguration is suitable to implement parameterized applica-tions. An application is said to be parameterized when some of its inputs, called parameters, are infrequently changing compared to the other inputs. Instead of im-plementing these parameter inputs as regular inputs, these inputs are implemented as constants, and the design is optimized for these constants. When the parameter values change, the design is re-optimized for the new constant values by recon-figuring the FPGA. A parameterized configuration contains bits that are not only static binary (0’s and 1’s) but also multi-valued Boolean functions of infrequently changing parameters. For specific parameter values, we can instantly derive spe-cialized configurations by evaluating the Boolean functions for the given parameter values. This technique is also called Dynamic Circuit Specialization (DCS).

DCS is a technique used to optimize parts of a parameterized application and switch between the specialized parts for the current specific conditions utilizing Partial Reconfiguration (PR) at run-time. This technique improves the functional density (number of computations that can be performed per unit area and unit time) of the FPGA. [37, 150]. Figure 2.8 demonstrates this method. Parameterized re-configuration is built on top of partial rere-configuration. Therefore, most parts in

Static

Partially Reconfigurable

region

configuration manager application

software

CPU

request

configuration database

Reconfiguration Controller

FPGA

Figure 2.7: Dynamic Partial Reconfiguration System

the system remain the same. The application software running on the CPU con-stantly monitors the (parameterized) inputs. Once a change in parameter value is detected, the specialization is performed by the configuration manager by evaluat-ing the Boolean functions (that are stored in the configuration database) for given parameter values, thus generating the specialized bitstreams. This is illustrated in Figure 2.9.

Tool Overview

The conventional FPGA tool flow cannot be used to generate parameterized con-figurations. Hence, an adapted version has been created, that is visualized in Fig-ure 2.10.

Synthesis: During synthesis, the HDL design is converted into a network of logic gates. The infrequently changing inputs in the HDL design are annotated as parameters. This annotation distinguishes between parameter inputs and regu-lar inputs. The parameter inputs are also a part of the Boolean network of logic gates produced after synthesis and are not treated differently in the synthesis step.

Static

Partially Reconfigurable

region

configuration manager application

software

CPU

request

configuration database

Reconfiguration Controller

FPGA

Figure 2.8: Parameterized Reconfiguration System

Hence, at this point any synthesis tool can be used, as long as it is able to handle the parameter annotations.

Technology Mapping: During technology mapping, the tool tries to find a net-work of cells that implements the Boolean netnet-work, in the same way as in conven-tional mapping. Here, the network is mapped in tuneable LUTs (TLUTs). These are virtual LUTs whose inputs are defined as the Boolean functions of the pa-rameter inputs instead of ones and zeros. To generate a papa-rameterized bitstream, authors of [55] changed the conventional mapping tool to a tuneable version, so that the Boolean functions of parameter inputs are mapped on to TLUTs or tune-able connections (TCONs). This process will eventually create the parameterized bitstream. This technology mapping algorithm can be integrated with the conven-tional Xilinx tool flow [12].

• TLUT: a virtual LUT of which the truth table entries are defined as Boolean functions of parameters instead of ones and zeros.

• TCON: a point-to-point connection which can be made or broken, based on

…. 0 1 a 1 0 a’ 1 1 a|b 1 0 0 b a&b 1 …

…. 0 1 1 1 0 0 1 1 1 1 0 0 0 0 1 …

…. 0 1 0 1 0 1 1 1 1 1 0 0 1 0 1 … Parameterised

Configuration Specialised

Configuration

a=1,b=0

a=0,b=1

Figure 2.9: Parameterized configurations include Boolean functions of parameters and they are evaluated into specialized configurations

the value of a Boolean function of parameters. It is implemented using the FPGA’s routing network. The parameterized configuration is derived from the Boolean function.

Placement and Routing As the parameters are already included in the LUT functionality through the Boolean functions, they are no longer present in the phys-ical implementation of the netlist so the entire netlist can be placed and routed as if the parameters where not present. Therefore, a conventional placer and router can be used.

Bitstream Generation The final output of the generic stage is the Template Con-figuration (TC) and Partial Parameterized ConCon-figuration (PPC). TC is a static bit-stream which contains static ones and zeros, which are used for configuring during the start of the FPGA. The PPC contains sets of Boolean functions of the parameter inputs. The PPC needs to undergo the specialization stage, along with parameter values to produce the specialized configuration. The specialization stage consists of a Specialized Configuration Generator (SCG), that takes the PPC and the pa-rameter values as inputs and evaluates the Boolean functions of papa-rameter inputs for given parameter values to produce a specialized configuration. During run time, the TLUTs are reconfigured by downloading the specialized configuration and thus accomplishing run time reconfiguration.

The SCG reconfigures the FPGA with the Internal Configuration Access Port (ICAP), that is a configuration interface. The ICAP swaps the specialized bit-streams into the FPGA configuration memory. Here, the HWICAP is used as a reconfiguration controller, encapsulates the ICAP primitive port of the FPGA and forms a controller that performs the swapping of specialized bitstreams via the ICAP. The bitstreams are accessed frame-by-frame. A frame is the smallest

Synthesis

packing &

Placement

Bitstream generation Technology

mapping TLUT/TCON

Partial Parameterised

Configuration

Route

Generic Stage

Specialization Stage parameterised

HDL

parameter values

evaluate Boolean function

Specialised Configuration

Figure 2.10: The two stage flow that supports parameterized configurations

addressable element of the FPGA configuration data. Each frame contains recon-figuration bits of tens of LUTs and has its unique frame address that can be used to point to the frame during the reconfiguration.