Parametric Models

In this section, we would present the models corresponding to each optimization metric, delay, leakage power, dynamic power and crosstalk noise. The delay and power models have been adapted from the literature, whereas a novel crosstalk noise model has been developed as part of this work. This crosstalk model identifies noise as a linear function of the sizes of the driver gates. The dis-

cussion focuses on identifying a relationship between these metrics, and formulates the mathematical programming models required for optimization. Also, the device level and interconnect process vari- ation are briefly visited.

3.3.1 Delay, Process Variations and Spatial Correlation

Reducing the size of a gate (say si), reduces the intrinsic gate capacitance of gate i, the power

consumption, and the fan-in load capacitances of i. In the linear delay model [95], the delay is modeled as a function of the gate sizes, as shown in (3.22).

di= ai− bisi+ ci

∑

sj (3.22)

where, di is the delay of gate i, si is the size of gate i, and sj corresponds to the sizes of all the fan-

out gates of i. The coefficients ai, bi, ci are empirically determined by extensive SPICE simulations

for each gate in the standard cell library for all combinations of sizes and fan-out. Specifically, bi

corresponds to the impact of channel length (Le f f) on the delay of a gate, and ci corresponds to the

impact of oxide thickness (tox)on the delay. Thus, the delay model incorporates the impact of device

process variations.

The uncertainty due to parameter variations in gate sizes is modeled according to (3.23), which is expressed in terms of nominal delay (di), and random parameters Xjand Xr, determining the correlated

and independent variations respectively.

D= di+ n

∑

j=1

djXj+ drXr (3.23)

Here, Xj models the principal components of correlated random variables with the corresponding dj

values evaluating the sensitivity of delay. Xr∼ N(0,1) models the random component of variations in

all process parameters lumped into a single term, and dris the standard deviation in delay due to these

random variations. The magnitude of djand dris determined by extensive simulations.

In the linear delay model, only the process variation effects in the gate sizes (Le f fand tox) are incor-

porated, but not the interconnect variations. The interconnect variations in today’s gigahertz designs are high, and can cause up to 25% variation in the clock skew, as shown in a paper by Liu et al. [68].

Also, these variations can not be incorporated in a simple nominal-worst case type of analysis. So, in this model, the effect of the interconnect variations are addressed in a mean-variance approach at the timing constraints level. The optimal delays identified through an unconstrained delay minimiza- tion as a first step in the optimization process are used as constraints for simultaneous optimization of power and crosstalk noise. We incorporate a conservative 10% variance around the mean of the best case timing values, corresponding to the interconnect variation effects.

The spatial correlations are modeled using a grid based correlation model proposed in [62]. Ac- cording to this modeling, the complete design is divided into different number of regions. The gates that are in same region are highly correlated and the variation effects on all of them are similar, whereas the variation effects on the gates that are in different regions are different and are less correlated. These effects are incorporated in (3.22) to evaluate the values of bi and ci, approximating the variations in

channel length and gate oxide thickness respectively.

3.3.2 Leakage and Dynamic Power

The power models proposed in [51] for dynamic and leakage power are adapted in our optimization formulation. The dynamic power dissipation Pd(i) of a gate i in each clock cycle tcdepends upon the

transition probability t pi, the power supply voltage Vdd, and the load capacitance Li. Load capacitance

on a gate i is given by (3.24).

Li= Wi+

∑

Ci(¯k)sk (3.24)

where Wi is the wire capacitance, and Ci(¯k) is the gate capacitance of the unit sized fan-out gate. The

equation for dynamic power dissipation can be given as (3.25).

Pd(i) = t pi

∑

Ci(¯k)skVdd2/(2tc) (3.25)

The average leakage power dissipation Pl(i) of gate i as a function of its size si, and the transition

probabilities are given by (3.26).

Pl(i) = [

∑

where, Il(i, r) is given as the leakage current of gate i for the input pattern r, P(i, r) is the leakage

power for gate i corresponding to the input pattern r, Il(¯i, r) is the leakage current for the unit sized

gate i and input pattern r, siis the size of gate i, and Vdd is power supply voltage.

From (3.25) and (3.26), it is identified that the leakage power of a gate is directly proportional to its size, and the dynamic power is proportional to the sum of the sizes of its fan-out gates.

3.3.3 Crosstalk Noise

The coupling capacitance effects in the circuits are substantial, and present a major threat to the reliability of the designs. They induce crosstalk noise on the coupled nets leading to timing yield failures. Although, the effect of crosstalk noise on a net can be reduced by using techniques like wire sizing, wire shielding, wire spacing, driver sizing (victim and aggressor), and receiver sizing (victim and aggressor), the most effective technique for reducing the crosstalk noise at the post-layout level is primarily driver sizing. In this technique, the driving gate of the net (often referred as the victim

net), and all other driver gates of the nets that have a coupling effect on that victim net (referred as aggressor nets) are sized. The up-sizing of the gates increases the signal strength on corresponding

net, and hence reduces the coupling effects.

Figure 3.2 shows a simple example of the noise on a net in a single victim-aggressor pair setting. Here, G1, G2, G3, and G4 are the gates sizes, C1 and C2 are the coupling capacitances between the wires, and Net1 and Net2 are the internal resistances. As discussed in [43], the major contributors to the crosstalk noise on a net are the sizes of the victim driver (G1), and aggressor driver gates (G2). If the size of the driving gate of the net is increased, the signal strength on the net increases, thereby reducing the coupling noise on the net. Also, if the size of the driver gate of the coupled net is decreased, the noise on the victim net decreases. However, such down-sizing will increase the noise on the coupled net. Similarly, the up-sizing of the victim driver will increase the noise on the coupled nets. Thus, the sizing has symmetric effects on the coupled nets, and a gate is an aggressor as well as a victim at the same time.

Figure 3.2 A coupling structure with single victim-aggressor pair setting. Here, G1, G2, G3, and G4 are the four gates, Net1 and Net2 are the two nets, and C1 and C2 correspond to the two half-coupling capacitances between the nets. For the victim net, Net1, G1 is the victim driver gate and G2 is the victim receiver gate. G3 is the aggressor driver gate for Net1 and G4 is the aggressor receiver gate for Net1.

The relationship between the sizes of the driving gates of the coupled nets is incorporated in formulating a simple crosstalk noise model. Here, the crosstalk noise on a net Niis given as (3.27)

Ni= Fi(

∑

(si− sj))∀si∈ n (3.27)

where, siis the size of the driving gate of the net, j is the set of all the coupled nets corresponding to

i, and sjis the size of the driver gate of the coupled net in an n-gate design. Hence, for every gate, the

noise on its fanout net is a function of the total cross-coupling capacitance on the net.

The effect of crosstalk noise in a circuit can also be minimized at another level by incorporating the noise margin constraints in the model. These constraints control that the maximum noise a net can

tolerate. In the present setting, the maximum tolerable noise on net j is given by (3.28).

Uj= H(

∑

(lj− uk))∀sk∈ coupled(sj) (3.28)

where, lj and uk correspond to the minimum and the maximum size of the gates available in the cell

library.