Variation Aware Gate Sizing

Several approaches for the optimization of delay, leakage power, dynamic power, and crosstalk noise in the presence of device process variations have been proposed in recent years. In this section, we discuss the state of the art statistical static timing analysis (SSTA) based and mathematical pro- gramming based approaches for variation aware gate sizing, on the basis of their strengths, as well as

Figure 2.5 Variation impact at different technology nodes [1]. As the process technology is moving toward lower technology nodes, the parametric variations are becoming a dominant factor in deter- mining the total impact of process variations.

limitations at the current technology nodes. The analysis and the next generation VLSI design chal- lenges make a strong case, for identifying new methods for multi-metric circuit optimization of the VLSI design problems.

2.4.1 Optimization Metrics

To analyze and optimize metrics like delay, power, yield, crosstalk noise etc. in the presence of process variations, several methods have been proposed in the literature. Since, this problem is addressed from a gate sizing perspective, the discussion is restricted to review only the variation aware gate sizing methods. Gate sizing is a simple yet effective technique for circuit optimization at the post- layout level, where-in the objective is to identify the optimal drive strength of each gate in the design. In Figure 2.6, a taxonomy of the recent works in gate sizing, classified according to the optimization metrics and the methodologies is presented.

• Power Optimization: Several works can be found in the literature on power optimization with

Figure 2.6 Taxonomy of the variation aware gate sizing works. The various works on the variation aware gate sizing are classified on the basis of optimization metrics and optimization methods.

2

[49–52]. In [47], a dynamic power minimization method is proposed with dynamic power identified as a function of the gate sizes in a stochastic programming model. Similarly, in [48], the authors have proposed a fuzzy mathematical programming based solution for dynamic power optimization. Leakage power minimization under process variations is performed using SSTA based methods [44, 45], in which continuous distributions are propagated through the paths instead of the deterministic values to find the closed form expressions for performance. In [46], a method to estimate the leakage current variation due to inter-die and intra-die gate length variations is presented.

• Crosstalk Noise Optimization: The power optimization methods are primarily single metric

models that do not consider the effect of gate sizing on other metrics such as crosstalk noise of the circuits. At the post-layout level, interconnect coupling effects can worsen the signal strength, leading to logic failures. Several techniques to reduce crosstalk noise have been pre- sented in the recent years. In [42], the authors propose a linear programming based formulation for transistor sizing to minimize crosstalk noise in circuits. In another approach [53,54], an yield driven Lagrangian Relaxation based method identifies the upper-bound on noise for each net as a noise constraint. The gates are iteratively sized-up to satisfy the timing and noise constraints, and a simple linear model is evaluated for crosstalk noise minimization. In a recent work [55], a stochastic game theoretic algorithm for post layout delay uncertainty and crosstalk noise op- timization considering spatial correlations [56, 57] is proposed. The non-linear crosstalk noise model used in this method is derived from [58], which accurately identifies a closer approxima- tion of the crosstalk noise.

• Delay Optimization: Additionally, the optimization of other important metrics like delay, timing

yield and binning yield have also been discussed widely [59–61]. However, this research is largely one-dimensional in the sense that these methods typically aim at optimizing specific metrics and often do not consider the fact that optimizing one metric may negatively impact the optimization of other metrics, leading to an inaccurate analysis of the complete design.

2.4.2 Optimization Methods

Several SSTA based approaches have successfully been applied for delay minimization or yield improvement problems [57, 62–64]. These approach intuitively model delay and yield optimization problems in a simple model. The SSTA based approaches, improve over the pessimistic worst-case corner based modeling [61] by performing a mean-variance analysis for the total circuit delay. How- ever, such approaches are essentially path based [65], and traditionally applied to optimize a single parameter. An assumption in a SSTA based technique is that the complete information about the vari- ation distribution of the design parameters is known, and the methodology is based on such assump- tions. Several works [6, 7] have assumed a Gaussian distribution. However, global sources of variation follow a log-normal distribution more closely [8, 9] as compared to the Gaussian distribution.

Mathematical programming based approaches have been widely investigated in the literature for

optimizing several metrics. An important aspect of mathematical programming approaches for circuit optimization is that any path based problem can be easily converted to the node based equivalent with some sub-optimality being introduced. A geometric programming (GP) approach has been proposed in [66] for delay optimization in the presence of process variations. Although, the approach is robust, the objective function and the constraints are required to be posynomial functions. Thus, modeling a generalized optimization problem in a GP framework requires converting each optimization function and the constraints in a posynomial form, and the problem can only be modeled for minimization of objectives.

In another approach for dynamic power minimization under delay constraints [47], the problem is modeled as a chance constrained stochastic program (CCP). Although CCP techniques can transform simple problems to their deterministic equivalent models, the transformation is extremely difficult for large scale problems. Also, the method is bounded by continuous distributions, and requires a number of operations to be performed iteratively at each node, thus involving higher run times. However, if the variation distribution information is available, the methodology can be modified to incorporate multiple metrics for optimization. Alternatively, the stochastic programming based statistical opti- mization techniques are reasonably fast, but more conservative in terms of yield, and hence provide lesser savings in terms of objective function optimizations. In a recent work [48], the dynamic power optimization problem considering process variations has been modeled in a fuzzy optimization frame-

work. Here, the stochastic parameters are modeled as fuzzy numbers, and a crisp non-linear problem is formulated to maximize the variation resistance (tolerance) of the circuit. The problem is then solved using commercially available optimization solvers. These methodologies typically aim at optimizing specific metrics and often do not consider the fact that optimizing one metric can negatively impact the optimization of other metrics, leading to an inaccurate analysis of the complete design. The La- grangian relaxation based methods [53] are limited to either up-sizing, or down-sizing the gates for the optimization.

A shortcoming in the proposed methods for gate sizing considering process variations arise from the fact that several methods [43, 47, 48] incorporate the effect of process variations due to only one design parameter, like gate sizes (due to channel length, and oxide thickness). The impact of inter- connect variations, which can cause 12-25% variations in the timing of the circuit, depending upon the design and implementation [67, 68] can not be ignored at the deep sub-nanometer level. The pro- cess variations can be modeled more accurately using complex and non-linear models that incorporate more parameters, and have higher accuracy [55]. The disadvantage of such a modeling lies in the implementation complexity.