Partial Evaluation of Floating Capacitive Coupling

The procedures described up to this point can be used to compute the moments of arbitrary interconnections of piecewise linear devices. If the network is free of loops and feedback

11_{Branch tearing is actually suboptimal with respect to node tearing in the sense that it may require more}

tearing variables. As illustrated by our example, tearing a branch can open up at most one loop while tearing a node can open up several. A similar result was proved by Sangiovanni-Vincentelli et al.[SVCC77]. However, in the context of a switch-level simulator, the implementation of branch tearing is slightly simpler.

12_{In fact, presently all our bipolar models also have zero DC base current although this is not actually a}

then the moments can be computed in linear time, otherwise the moments are computed with reduced efficiency. In either case, the moments are computed exactly (except for the numerical error introduced by executing the algorithms on a real computer).

However, under certain circumstances it may be necessary to give up trying to compute the moments exactly.13 _{In particular, the inclusion of floating capacitors into device models}

introduces an efficiency problem. To illustrate, examine the cascade of three CMOS inverters shown in Figure 69. Assume that the circuit has settled and consider the

C2 C1 n2 (0->1) n1 (1->0) T6 T2 _{C3 C4} n3 (1->0) C5 in (0->1) T1 T3 T4 T5

Figure 69: Clusters Coupled by Floating Capacitors.

sequence of events that follows T2 turning on. First note that were it not for the floating capacitors C1 and C2, nodes n1, n2, and n3 would reside in three different groups. This is because T3 - T6 are initially biased into either the off or linear regions which exhibit zero gain from the gate to the source and drain. However C1 and C2 couple all three nodes into the same group. Although the efficiency of moment computation is still

O

n

cycles can be introduced by floating capacitors) we must recompute the response of many more nodes than would seem necessary. Intuitively we would expect that the effect of T2 switching upon n2 (coupled through 1 level of floating capacitors) to be quite small relative to the logic swing, and the effect on n3 (coupled through 2 levels of floating capacitors) to be negligible. Otherwise the logic gate abstraction would never have been found to be useful. However, with our present moment computation algorithm, floating capacitors can potentially couple all nodes in a circuit thereby eliminating the ability to take advantage of circuit latency.

A simple solution is to allow a group to expand through only a limited number of levels of floating capacitors. Nodes sufficiently distant (in terms of the number of levels of

floating capacitors) from the switching event are presumed to be essentially unaffected by the event. For our example, if the maximum number of levels is set to 1, then only n2 would be brought into the same group as n1. However, when the expansion process is truncated there may be some capacitors that only have one terminal belonging to the group. In that case the terminal outside the group is considered to be driven by a (possibly time varying) voltage source that has the waveform presently on the node. That waveform is otherwise undisturbed by the event. For our example, C2 is treated as if its right terminal were driven by a voltage source having n3’s present waveform. Node n3 retains whatever waveform it had prior to T2 switching.

Our initial experience is that this procedure works well. Figure 70 plots the response of a 9 stage ECL ring oscillator when Mom expands groups through various numbers of levels of floating capacitors. In each case the output of Mom using the Level-2 bipolar model (which includes parasitic floating capacitors and resistors) is compared with that of SPICE using an identical piecewise linear model. Table 3 gives the switching delay error for each case. The figure and table show that the largest change in accuracy is obtained by

capacitor levels 0 1 2 unlimited % switching delay error 3.5 0.3 0.7 1.8 run time (seconds) 2.3 6.2 10.0 19.5 nodes per group 7.9 24.6 54.9 108 # waveform computations 869 2710 4127 7960 Table 3: Decrease in Efficiency with Increasing Capacitor Levels. expanding the group through just 1 level of floating capacitors.14

The table also shows the super-linear growth of execution time with increasing numbers of levels. This super-linear growth can be explained. First note that the number of events doesn’t change. Thus the execution time is roughly proportional to the number of waveform computations and hence the average size of a group. Also note that because of the nodes and

14_{Mom and SPICE piecewise linear simulations appear to be converging to slightly different waveforms.}

The most obvious source of error is the waveform approximation. However, there are other possible sources of error. For practical reasons, it is not actually possible for Mom and SPICE to simulate exactly identical piecewise linear models. Small parasitic conductances and capacitances must be added to SPICE’s piecewise linear models in order to aid convergence of the numerical integration. Hysteresis (+/- 1mV) must be added to Mom’s piecewise linear models to enhance the stability of event scheduling. Finally, experimentation with simple circuits that could be solved analytically indicate that SPICE may generate errors as large as 0.3%.

time 0 2 4 6 8 10 nS -0.6 -0.5 -0.4 -0.3 -0.2 -0.1 0.0 0.1 V Mom SPICE (a) 0 Levels. time 0 2 4 6 8 10 nS -0.6 -0.5 -0.4 -0.3 -0.2 -0.1 0.0 0.1 V Mom SPICE (b) 1 Level. time 0 2 4 6 8 10 nS -0.6 -0.5 -0.4 -0.3 -0.2 -0.1 0.0 0.1 V Mom SPICE (c) 2 Levels. time 0 2 4 6 8 10 nS -0.6 -0.5 -0.4 -0.3 -0.2 -0.1 0.0 0.1 V Mom SPICE (d) Unlimited Levels. Figure 70: Limited Levels of Floating Capacitors.

coupling introduced by the bipolar parasitics the fine grain of the interconnection network resembles a mesh. If the number of levels is modeled by the radius of a circle, and the number of nodes in a group by the area of the circle then one would expect a roughly quadratic initial growth of the group size with the number of levels.

Finally, note that for our small example a maximum speedup of only 8.5:1 is achieved. This seems consistent with the expectation that at any instant in time only one or two of the nine stages of the ring is actively switching. However, larger circuits often exhibit much more latency, and one might expect correspondingly greater speedups for them.

5.8

Summary

Moment computation can dominate the cost of waveform estimation. To compute moments, switch-level simulators use RC tree analysis which is efficient because it takes advantage of the tree-like topology of most circuits. We generalize RC tree analysis along two dimensions. First, tree analysis is extended to apply when transistor models are generalized from resistors to piecewise linear devices. This generalization retains the efficiency of RC tree analysis for the transistor-capacitor trees found in MOS circuits and the current steering trees found in ECL circuits. Second, tearing is used to handle non-tree topologies and feedback. The advantage of combining a tree analysis with tearing is that most circuits are trees and hence can be analyzed efficiently. The cost of analyzing more general non-tree topologies is paid only when it is needed.

The addition of floating capacitors to device models can degrade simulation efficiency because floating capacitors can potentially couple together all nodes in the circuit thereby eliminating the ability of the simulator to take advantage of circuit latency. However, in digital circuits there is rarely any significant coupling through multiple levels of floating capacitors. Thus, repartitioning of the circuit can be achieved by ignoring coupling through all but a limited number of levels of floating capacitors.