The driver performs the following transactions with status of the transactions displayed in the ModelSim simulation message window:
• Various configuration reads and writes to the Avalon-MM Stratix V Hard IP for PCI Express in your system after the link is initialized
• Register writes, reads and compares to both functions
• Burst memory writes, reads, and compares to both functions
The following example shows the transcript from a successful simulation run.
Example 4-1: Transcript from ModelSim Simulation of Gen1 x4 Endpoint
# INFO: 464 ns Completed initial configuration of Root Port.
# 495000: INFO: top_tb.top_inst_reset_bfm.reset_deassert: Reset deasserted
# INFO: 3657 ns RP LTSSM State: DETECT.ACTIVE
# INFO: 4425 ns RP LTSSM State: POLLING.ACTIVE
# INFO: 17257 ns RP LTSSM State: DETECT.QUIET
# INFO: 20473 ns RP LTSSM State: DETECT.ACTIVE
# INFO: 21193 ns RP LTSSM State: POLLING.ACTIVE
# INFO: 29909 ns EP LTSSM State: DETECT.ACTIVE
# INFO: 30949 ns EP LTSSM State: POLLING.ACTIVE
# INFO: 33957 ns EP LTSSM State: POLLING.CONFIG
# INFO: 34025 ns RP LTSSM State: DETECT.QUIET
# INFO: 37241 ns RP LTSSM State: DETECT.ACTIVE
# INFO: 37961 ns RP LTSSM State: POLLING.ACTIVE
# INFO: 39945 ns RP LTSSM State: POLLING.CONFIG
# INFO: 41033 ns RP LTSSM State: CONFIG.LINKWIDTH.START
# INFO: 41445 ns EP LTSSM State: CONFIG.LINKWIDTH.START
# INFO: 41765 ns EP LTSSM State: CONFIG.LINKWIDTH.ACCEPT
# INFO: 42057 ns RP LTSSM State: CONFIG.LINKWIDTH.ACCEPT
# INFO: 42249 ns RP LTSSM State: CONFIG.LANENUM.WAIT
# INFO: 42789 ns EP LTSSM State: CONFIG.LANENUM.WAIT
# INFO: 43033 ns RP LTSSM State: CONFIG.LANENUM.ACCEPT
# INFO: 43109 ns EP LTSSM State: CONFIG.LANENUM.ACCEPT
# INFO: 43225 ns RP LTSSM State: CONFIG.COMPLETE
# INFO: 43685 ns EP LTSSM State: CONFIG.COMPLETE
# INFO: 44953 ns RP LTSSM State:CONFIG.IDLE
# INFO: 47941 ns EP LTSSM State: CONFIG.IDLE
# INFO: 48089 ns RP LTSSM State: L0
# INFO: 48133 ns EP LTSSM State: L0
# INFO: 48226 ns Configuring Bus 000, Device 000, Function 00
# INFO: 48226 ns RP Read Only Configuration Registers:
# INFO: 48226 ns Vendor ID: 1556
# INFO: 48226 ns Device ID: 5555
# INFO: 48226 ns Revision ID: 00
# INFO: 48226 ns Class Code: 040000
# INFO: 48706 ns ECRC Check Capable: Supported
# INFO: 48706 ns ECRC Generation Capable: Supported
# INFO: 48738 ns RP PCI Express Slot Capability
Partial Transcript for Configuration Space Bypass Simulation 4-11 UG-01097_avst
December 2013
# INFO: 48738 ns Power Controller: Not Present
# INFO: 48738 ns MRL Sensor: Not Present
# INFO: 48738 ns Attention Indicator: Not Present
# INFO: 48738 ns Power Indicator: Not Present
# INFO: 48738 ns Hot-Plug Surprise: Not Supported
# INFO: 48738 ns Hot-Plug Capable: Not Supported
# INFO: 48738 ns Slot Power Limit Value: 0
# INFO: 48738 ns Slot Power Limit Scale: 0
# INFO: 48738 ns Physical Slot Number: 0
# INFO: 48738 ns Activity_toggle flag is set
# INFO: 48802 ns RP PCI Express Link Status Register (0081):
# INFO: 48802 ns RP PCI Express Max Link Speed (0002):
# INFO: 48802 ns RP PCI Express Current Link Speed (0001):
# INFO: 48802 ns Negotiated Link Width: x8
# INFO: 48802 ns Slot Clock Config: Local Clock Used
# INFO: 48834 ns Current Link Speed: 2.5GT/s
# INFO: 48889 ns RP LTSSM State: RECOVERY.RCVRLOCK
# INFO: 49669 ns EP LTSSM State: RECOVERY.RCVRLOCK
# INFO: 50501 ns EP LTSSM State: RECOVERY.RCVRCFG
# INFO: 51209 ns RP LTSSM State: RECOVERY.RCVRCFG
# INFO: 48889 ns RP LTSSM State: RECOVERY.RCVRLOCK
# INFO: 53669 ns EP LTSSM State: RECOVERY.SPEED
# INFO: 54721 ns RP LTSSM State: RECOVERY.RCVRLOCK
# INFO: 54746 ns Wait for Link to enter L0 after negotiated to
# the expected speed of EP Target Link Speed 0002):
# INFO: 53337 ns RP LTSSM State: RECOVERY.SPEED
# INFO: 55235 ns EP LTSSM State: RECOVERY.RCVRLOCK
# INFO: 56299 ns EP LTSSM State: RECOVERY.RCVRCFG
# INFO: 57163 ns RP LTSSM State: RECOVERY.RCVRCFG
# INFO: 57707 ns RP LTSSM State: RECOVERY.IDLE
# INFO: 57979 ns EP LTSSM State: RECOVERY.IDLE
# INFO: 58035 ns RP LTSSM State: L0
# INFO: 58075 ns EP LTSSM State: L0
# INFO: 58090 ns New Link Speed: 5.0GT/s
# INFO: 58106 ns RP PCI Express Link Control Register (0000):
# INFO: 58106 ns Common Clock Config: Local Clock
# INFO: 70602 ns Completed configuration of Endpoint BARs.
# INFO: 70602 ns TASK:my_test Setup
# INFO: 70602 ns TASK:my_test Write to 32bit register at
# addr = 0x0 with wdata=0xBABEFACE
# INFO: 70610 ns TASK:my_test Read from 32bit register at
# addr 0x00000000
# INFO: 71298 ns TASK:my_test Register compare matches!
# INFO: 71298 ns TASK:my_test Write to 32bit register at
# 0x00000004 Actual 0x12345678
# INFO: 71306 ns TASK:my_test => 1.22 Read from 32bit register
# at addr = 0x00000004
# INFO: 71994 ns TASK:my_test => 1.23 Register compare matches!
# INFO 71994 ns TASK:my_test => 2.11 Fill write memory with
# QWORD_INC pattern
# INFO: 71994 ns TASK:my_test Memory write burst at addr=0x00
# with wdata=0x10203040
# INFO: 72002 ns TASK:my_test => 2.21 Memory Read burst
UG-01097_avst Partial Transcript for Configuration Space Bypass Simulation
4-12 December 2013
# INFO: 72690 ns TASK:my_test Memory write burst at addr=0x04
# with wdata=0x10203040
# INFO: 72698 ns TASK:my_test Memory Read burst
# INFO: 73354 ns TASK:my_test Memory write burst at addr=0x08
# with wdata=0x10203040
# INFO: 73362 ns TASK:my_test => 2.21 Memory Read burst
# INFO: 74178 ns TASK:my_test Memory write burst at addr=0x0C
# with wdata=0x10203040
# INFO: 88154 ns Enumerate EP function = 0x01
# INFO: 88154 ns cfgbp_enum_config_space Setup config space
# for func = 00000001
# INFO: 88154 ns Config Read # INFO: 88946 ns CfgRD at
# addr =0x00000000 returns data = 0xE0011172
# INFO: 88946 ns Set Bus_Master and Memory_Space_Enable
# bit in Command register00000001
# INFO: 88946 ns Read Modified WRite to config register
# = 0x00000004 in func = 0x00000001
# INFO: 115370 ns TASK:my_test; 2.21 Memory Read burst
# SUCCESS: Simulation stopped due to successful completion!
# Break in Function ebfm_log_stop_sim at
# /..//top_tb/simulation/submodules//altpcietb_bfm_log.v line 78
# INFO: 88946 ns Set Bus_Master and Memory_Space_Enable bit
# in Command register00000001
# INFO: 88946 ns Read Modified WRite to config register =
# 0x00000004 in func = 0x00000001
# INFO: 88946 ns Set Bus_Master and Memory_Space_Enable bit
# in Command register00000001
# INFO: 88946 ns Read config reg
# INFO: 89738 ns Original config read data = 00000000
# INFO: 89738 ns Config write with data = 00000006
# INFO: 91338 ns After cfg_rd_modified_wr, config_data
# = 0x00000006
# INFO: 92938 ns CfgRD at BAR0 (addr =0x00000010) returns
# data = 0xFFF0000C
# INFO: 94530 ns CfgRD at addr =0x00000010 returns data
# = 0x8000000C
# INFO: 97658 ns BAR Address Assignments:
# INFO: 97658 ns BAR Size Assigned Address Type
# INFO: 97658 ns BAR1:0 1 MBytes 00000001 00000000 Prefetchable
# INFO: 97658 ns BAR2 Disabled
# INFO: 97658 ns BAR3 Disabled
# INFO: 97658 ns BAR4 Disabled
# INFO: 97658 ns BAR5 Disabled
# INFO: 97658 ns ExpROM Disabled
# INFO: 98794 ns Completed configuration of Endpoint BARs.
# INFO: 98794 ns TASK:my_test Setup
# INFO: 98794 ns TASK:my_test Write to 32bit register at 0x000000
# with wdata=0xBABEFACE
# INFO: 98802 ns TASK:my_test 1.12 Read from 32bit register
# at addr = 0x00000000
# INFO: 9490 ns TASK:my_test 1.13 Register compare matches!
# INFO: 115370 ns TASK:my_test 2.21 Memory Read burst
Partial Transcript for Configuration Space Bypass Simulation 4-13 UG-01097_avst
December 2013
# SUCCESS: Simulation stopped due to successful completion!
# Break in Function ebfm_log_stop_sim at
# ./..//top_tb/simulation/submodules//altpcietb_bfm_log.v
# line 78
UG-01097_avst Partial Transcript for Configuration Space Bypass Simulation
4-14 December 2013